# US 11,112,820 B1 · Method for transmitting signals between domains having different clocks, circuit, and electronic apparatus thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,112,820 B1 - Document ID: US11112820B1 - Status: Granted - Kind: B1 - Application number: 17/021,584 - Filed: 2020-09-15 - Granted: 2021-09-07 - Earliest claimed: 2020-07-03 - Assignees: Hon Hai Precision Industry Co., Ltd. - Applicants: Hon Hai Precision Industry Co., Ltd. - Inventors: Yi-Lang Kao - Web page: https://patentgrep.com/patent/US11112820B1 ## CPC - G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators} - G06F 1/10: Distribution of clock signals {, e.g. skew} - G06F 13/24: using interrupt (G06F13/32 takes precedence) - H03K 3/037: Bistable circuits - H03K 5/1534: Transition or edge detectors - H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) - H04L 7/02: Speed or phase control by the received code signals, the signals containing no special synchronisation information {(H04L7/0075 takes precedence)} - H04L 7/0045: {Correction by a latch cascade} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A signal transmitting circuit providing compatibility and stability in signal transmissions across domains with different clock frequencies includes an edge detection circuit, a flip circuit, a synchronization circuit, and an edge extraction circuit. The edge detection circuit detects an edge of an initial interrupt signal and generates an event trigger signal in a faster clock domain. The flip circuit converts the event trigger signal into an edge signal. The synchronization circuit synchronizes the edge signal under a slower clock domain and generates a synchronization signal. The edge extraction circuit generates a trigger signal based on the synchronization signal in the slower clock domain to a target circuit in the slower clock domain. A method and an electronic apparatus related to the signal transmitting circuit are also disclosed. ## Claims ### Claim 1 A method for transmitting signals between different clock domains used in an electronic apparatus, the electronic apparatus comprises an edge detection circuit and a pulse synchronization circuit; the method comprising: receiving an initial interrupt signal in a faster clock domain by the edge detection circuit; detecting an edge of the initial interrupt signal and generating an event trigger signal by the edge detection circuit; converting the event trigger signal into an edge signal by the pulse synchronization circuit; synchronizing the edge signal under a slower clock domain and generating a synchronization signal by the pulse synchronization circuit; and generating a trigger signal based on the synchronization signal in the slower clock domain by the pulse synchronization circuit to a target circuit in the slower clock domain. ### Claim 2 (depends on 1) The method of claim 1, wherein the edge detection module comprises first trigger, a second trigger, and a logic circuit; a signal input terminal of the first trigger receives the initial interrupt signal; a clock terminal of the first trigger receives a first clock signal; an output terminal of the first trigger is electrically connected with the second trigger and the logic circuit; a signal input terminal of the second trigger is electrically connected with the output terminal of the first trigger; a clock terminal of the second trigger receives the first clock signal; an output terminal of the second trigger is electrically connected with an inverting input terminal of the logic circuit; an input terminal of the logic circuit is electrically connected with the output terminal of the first trigger; an output terminal of the logic circuit is electrically connected to the pulse synchronization circuit. ### Claim 3 (depends on 2) The method of claim 2, wherein the event trigger signal is a single pulse signal; the logic circuit is a AND gate. ### Claim 4 (depends on 2) The method of claim 2, wherein the pulse synchronization circuit comprises a flip circuit, a synchronization circuit, and an edge extraction circuit; the flip circuit comprises a multiplexer and a third trigger; an input terminal of the multiplexer is electrically connected with the output terminal of the logic circuit; an output terminal of the multiplexer is electrically connected with an input terminal of the third trigger; a clock terminal of the third trigger receives the first clock signal; an output terminal of the third trigger is electrically connected with the synchronization circuit. ### Claim 5 (depends on 4) The method of claim 4, wherein the synchronization circuit comprises a fourth trigger and a fifth trigger; an input terminal of the fourth trigger is electrically connected with the output terminal of the third trigger; a clock terminal of the fourth trigger receives a second clock signal; an output terminal of the fourth trigger is electrically connected with an input terminal of the fifth trigger; a clock terminal of the fifth trigger receives the second clock signal; an output terminal of the fifth trigger is electrically connected with the edge extraction circuit; a frequency of the first clock signal is higher than a frequency of the second clock signal. ### Claim 6 (depends on 5) The method of claim 5, wherein the edge extraction circuit comprises a sixth trigger and a second logic circuit; an input terminal of the sixth trigger is electrically connected with the output terminal of the fifth trigger; a clock terminal of the sixth trigger receives the second clock signal; an output terminal of the sixth trigger is electrically connected with a second input terminal of the second logic circuit; a first input terminal of the logic circuit is electrically connected with the output terminal of the fifth trigger; the second logic circuit is an exclusive-OR gate. ### Claim 7 A signal transmitting circuit comprising: an edge detection circuit, configured to detect an edge of an initial interrupt signal and generate an event trigger signal in a faster clock domain; a flip circuit, configured to convert the event trigger signal into an edge signal a synchronization circuit, configured to synchronize the edge signal under a slower clock domain and generate a synchronization signal; and an edge extraction circuit, configured to generate a trigger signal based on the synchronization signal in the slower clock domain to a target circuit in the slower clock domain. ### Claim 8 (depends on 7) The signal transmitting circuit of claim 7, wherein the edge detection module comprises first trigger, a second trigger, and a logic circuit; a signal input terminal of the first trigger receives the initial interrupt signal; a clock terminal of the first trigger receives a first clock signal; an output terminal of the first trigger is electrically connected with the second trigger and the logic circuit; a signal input terminal of the second trigger is electrically connected with the output terminal of the first trigger; a clock terminal of the second trigger receives the first clock signal; an output terminal of the second trigger is electrically connected with an inverting input terminal of the logic circuit; an input terminal of the logic circuit is electrically connected with the output terminal of the first trigger; an output terminal of the logic circuit is electrically connected to the pulse synchronization circuit. ### Claim 9 (depends on 8) The signal transmitting circuit of claim 8, wherein the event trigger signal is a single pulse signal; the logic circuit is a AND gate. ### Claim 10 (depends on 8) The signal transmitting circuit of claim 8, wherein the flip circuit comprises a multiplexer and a third trigger; an input terminal of the multiplexer is electrically connected with the output terminal of the logic circuit; an output terminal of the multiplexer is electrically connected with an input terminal of the third trigger; a clock terminal of the third trigger receives the first clock signal; an output terminal of the third trigger is electrically connected with the synchronization circuit. ### Claim 11 (depends on 10) The signal transmitting circuit of claim 10, wherein the synchronization circuit comprises a fourth trigger and a fifth trigger; an input terminal of the fourth trigger is electrically connected with the output terminal of the third trigger; a clock terminal of the fourth trigger receives a second clock signal; an output terminal of the fourth trigger is electrically connected with an input terminal of the fifth trigger; a clock terminal of the fifth trigger receives the second clock signal; an output terminal of the fifth trigger is electrically connected with the edge extraction circuit; a frequency of the first clock signal is higher than a frequency of the second clock signal. ### Claim 12 (depends on 11) The signal transmitting circuit of claim 11, wherein the edge extraction circuit comprises a sixth trigger and a second logic circuit; an input terminal of the sixth trigger is electrically connected with the output terminal of the fifth trigger; a clock terminal of the sixth trigger receives the second clock signal; an output terminal of the sixth trigger is electrically connected with a second input terminal of the second logic circuit; a first input terminal of the logic circuit is electrically connected with the output terminal of the fifth trigger; the second logic circuit is an exclusive-OR gate. ### Claim 13 An electronic apparatus comprising: a signal transmitting circuit, configured to receive an initial interrupt signal; the signal transmitting circuit comprising: an edge detection circuit, configured to detect an edge of an initial interrupt signal and generate an event trigger signal in a faster clock domain; a flip circuit, configured to convert the event trigger signal into an edge signal a synchronization circuit, configured to synchronize the edge signal under a slower clock domain and generate a synchronization signal; and an edge extraction circuit, configured to generate a trigger signal based on the synchronization signal in the slower clock domain to a target circuit in the slower clock domain. ### Claim 14 (depends on 13) The electronic apparatus of claim 13, wherein the edge detection module comprises first trigger, a second trigger, and a logic circuit; a signal input terminal of the first trigger receives the initial interrupt signal; a clock terminal of the first trigger receives a first clock signal; an output terminal of the first trigger is electrically connected with the second trigger and the logic circuit; a signal input terminal of the second trigger is electrically connected with the output terminal of the first trigger; a clock terminal of the second trigger receives the first clock signal; an output terminal of the second trigger is electrically connected with an inverting input terminal of the logic circuit; an input terminal of the logic circuit is electrically connected with the output terminal of the first trigger; an output terminal of the logic circuit is electrically connected to the pulse synchronization circuit. ### Claim 15 (depends on 14) The electronic apparatus of claim 14, wherein the event trigger signal is a single pulse signal; the logic circuit is a AND gate. ### Claim 16 (depends on 14) The electronic apparatus of claim 14, wherein the flip circuit comprises a multiplexer and a third trigger; an input terminal of the multiplexer is electrically connected with the output terminal of the logic circuit; an output terminal of the multiplexer is electrically connected with an input terminal of the third trigger; a clock terminal of the third trigger receives the first clock signal; an output terminal of the third trigger is electrically connected with the synchronization circuit. ### Claim 17 (depends on 16) The electronic apparatus of claim 16, wherein the synchronization circuit comprises a fourth trigger and a fifth trigger; an input terminal of the fourth trigger is electrically connected with the output terminal of the third trigger; a clock terminal of the fourth trigger receives a second clock signal; an output terminal of the fourth trigger is electrically connected with an input terminal of the fifth trigger; a clock terminal of the fifth trigger receives the second clock signal; an output terminal of the fifth trigger is electrically connected with the edge extraction circuit. ### Claim 18 (depends on 13) The electronic apparatus of claim 13, wherein a frequency of a first clock signal in the faster clock domain is higher than a frequency of a second clock signal in the slower clock domain. ### Claim 19 (depends on 17) The electronic apparatus of claim 17, wherein the edge extraction circuit comprises a sixth trigger and a second logic circuit; an input terminal of the sixth trigger is electrically connected with the output terminal of the fifth trigger; a clock terminal of the sixth trigger receives the second clock signal; an output terminal of the sixth trigger is electrically connected with a second input terminal of the second logic circuit; a first input terminal of the logic circuit is electrically connected with the output terminal of the fifth trigger. ### Claim 20 (depends on 19) The electronic apparatus of claim 19, wherein the second logic circuit is an exclusive-OR gate.