# US 11,112,818 B2 · Reception apparatus with clock failure recovery and transmission system including the same

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- Number: US 11,112,818 B2
- Document ID: US11112818B2
- Status: Granted
- Kind: B2
- Application number: 16/654,271
- Filed: 2019-10-16
- Published: 2020-05-21
- Granted: 2021-09-07
- Earliest claimed: 2018-11-15
- Assignees: MagnaChip Semiconductor, Ltd.
- Applicants: MagnaChip Semiconductor, Ltd.
- Inventors: Su Hyun Kim; Sang Kyung Kim; Gil Sung Roh
- Web page: https://patentgrep.com/patent/US11112818B2

## CPC

- G06F 1/08: Clock generators with changeable or programmable clock frequency
- H04L 7/0008: {Synchronisation information channels, e.g. clock distribution lines}
- G06F 11/0757: {by exceeding a time limit, i.e. time-out, e.g. watchdogs}
- G06F 11/0772: {Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers}
- G06F 11/0793: {Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40)}
- G06F 11/3013: {where the computing system is an embedded system, i.e. a combination of hardware and software dedicated to perform a certain function in mobile devices, printers, automotive or aircraft systems (testing or monitoring of control systems or parts thereof G05B23/02)}
- G06F 11/3058: {Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206)}
- H03C 3/0966: {modulating the reference clock}
- H03L 7/07: using several loops, e.g. for redundant clock signal generation
- H03L 7/0802: {the loop being adapted for reducing power consumption (H03L7/14 takes precedence)}
- G06F 11/3062: {where the monitored property is the power consumption (power management in a computing system G06F1/3203)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03C: MODULATION (masers or lasers H01S; coding, decoding or code conversion H03M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A reception apparatus communicating with a transmission apparatus with a clock lane and a data lane. The reception apparatus comprises a clock lane control circuit configured to determine the operation mode of the clock lane based on a clock signal transmitted through the clock lane, and performing an operation based on the determined operation mode of the clock lane, and a data lane control circuit configured to determine the operation mode of the data lane based on a data signal transmitted from the transmission apparatus, and performing an operation based on the determined operation mode of the data lane, and the clock lane control circuit is configured to set the operation mode of the clock lane to a high-speed mode, when the operation mode of the data lane is switched from a low-power mode to the high-speed mode.

## Claims

### Claim 1

A reception apparatus communicating with a transmission apparatus, the reception apparatus comprising:
a clock lane control circuit configured to determine an operation mode of a clock lane based on a clock signal transmitted through the clock lane, and perform an operation based on the determined operation mode of the clock lane; and
a data lane control circuit configured to determine an operation mode of a data lane based on a data signal transmitted from the transmission apparatus, and perform an operation based on the determined operation mode of the data lane,
wherein the clock lane control circuit is further configured to:
detect that the operation mode of the data lane has been switched from a low-power mode to a high-speed mode,
generate an interrupt signal based on a result of the detection, and
set the operation mode of the clock lane to the high-speed mode in response to the generated interrupt signal regardless of the operation mode of the clock lane.

### Claim 2 (depends on 1)

The reception apparatus of claim 1, wherein the data lane control circuit is further configured to output a state signal indicating the operation mode of the data lane, and
wherein the clock lane control circuit is further configured to set the operation mode of the clock lane to the high-speed mode in response to the state signal.

### Claim 3 (depends on 2)

The reception apparatus of claim 2, wherein the clock lane control circuit comprises a clock lane finite state machine (FSM) configured to control the operation mode of the clock lane, and
wherein the clock lane FSM is configured to:
switch the operation mode of the clock lane from the low-power mode to the high-speed mode, when a level of the clock signal indicates a high-speed mode entering sequence, and
set the operation mode of the clock lane to the high-speed mode when the operation mode of the data lane is switched from the low-power mode to the high-speed mode, when the level of the clock signal does not indicate the high-speed mode entering sequence.

### Claim 4 (depends on 3)

The reception apparatus of claim 3, wherein the data lane control circuit comprises a data lane FSM configured to control the operation mode of the data lane, and
wherein the data lane FSM is configured to:
monitor a level of the data signal, and generate a state signal indicating the operation mode of the data lane according to a result of the monitoring, and
output the generated state signal to the clock lane FSM.

### Claim 5 (depends on 1)

The reception apparatus of claim 1, wherein the clock lane control circuit is further configured to generate a high-speed internal clock signal corresponding to the high-speed mode, and
wherein the data lane control circuit is further configured to process the data signal by being synchronized to the high-speed internal clock signal, and generate the processed data signal.

### Claim 6 (depends on 2)

The reception apparatus of claim 2, wherein the clock lane control circuit is configured to generate the interrupt signal in response to the state signal.

### Claim 7 (depends on 6)

The reception apparatus of claim 6, wherein the clock lane control circuit is further configured to generate the interrupt signal while the data lane operates in the high-speed mode.

### Claim 8 (depends on 1)

The reception apparatus of claim 1, wherein the clock lane control circuit comprises a noise sensing circuit configured to detect external noise occurring on the clock lane, and the clock lane control circuit is further configured to:
determine whether the operation mode of the data lane is switched from the low-power mode to the high-speed mode, when the external noise is detected by the noise sensing circuit, and
set the operation mode of the clock lane to the high-speed mode, when the operation mode of the data lane is switched from the low-power mode to the high-speed mode.

### Claim 9

A communication method between a reception apparatus and a transmission apparatus, the method comprising:
determining an operation mode of a clock lane based on a clock signal transmitted through the clock lane, and performing an operation based on the determined operation mode of the clock lane;
determining an operation mode of the data lane based on a data signal transmitted from the transmission apparatus, and performing an operation based on the determined operation mode of the data lane;
setting the operation mode of the clock lane to a high-speed mode based on an interrupt signal generated when the operation mode of the data lane is switched from a low-power mode to the high-speed mode regardless of the operation mode of the clock lane;
generating a high-speed internal clock signal corresponding to the high-speed mode when the clock lane operates in the high-speed mode; and
processing the data signal by being synchronized to the high-speed internal clock signal and generating the processed data signal.

### Claim 10 (depends on 9)

The method of claim 9, wherein the setting the operation mode of the clock lane to the high-speed mode comprises:
generating a state signal indicating the operation mode of the data lane; and
setting the operation mode of the clock lane to the high-speed mode in response to the state signal.

### Claim 11 (depends on 10)

The method of claim 10, wherein the operating method further comprises:
switching the operation mode of the clock lane from the low-power mode to the high-speed mode, when a level of the clock signal indicates a high-speed mode entering sequence; and
setting the operation mode of the clock lane to the high-speed mode when the operation mode of the data lane is switched from the low-power mode to the high-speed mode, when the level of the clock signal does not indicate the high-speed mode entering sequence.

### Claim 12 (depends on 9)

The method of claim 9, wherein the setting the operation mode of the clock lane to the high-speed mode comprises:
detecting that the operation mode of the data lane is switched from the low-power mode to the high-speed mode;
generating the interrupt signal based on a result of the detection; and
setting the operation mode of the clock lane to the high-speed mode in response to the generated interrupt signal.

### Claim 13 (depends on 12)

The method of claim 12, wherein the generating the interrupt signal comprises generating the interrupt signal while the data lane operates according to the high-speed mode.

### Claim 14 (depends on 9)

The method of claim 9, wherein the setting the operation mode of the clock lane to the high-speed mode comprises:
detecting external noise occurring on the clock lane;
determining whether the operation mode of the data lane is switched from the low-power mode to the high-speed mode, when the external noise has been detected; and
setting the operation mode of the clock lane to the high-speed mode, when the operation mode of the data lane is switched to the high-speed mode.

### Claim 15

A transmission system, comprising:
a transmission apparatus;
a reception apparatus; and
a clock lane and at least one data lane connected between the transmission apparatus and the reception apparatus,
wherein the clock lane and the at least one data lane are configured to operate based on any one mode of a low-power mode and a high-speed mode, respectively,
wherein the reception apparatus comprises:
a clock lane control circuit configured to determine an operation mode of the clock lane based on a clock signal transmitted through the clock lane, and perform an operation based on the determined operation mode of the clock lane; and
a data lane control circuit configured to:
determine the operation mode of the at least one data lane based on a data signal transmitted from the transmission apparatus,
output a state signal indicating the operation mode of the data lane, and
perform an operation based on the determined operation mode of the at least one data lane, and
wherein the clock lane control circuit is further configured to:
determine whether the operation mode of the data lane has been switched from the low-power mode to the high-speed mode based on the state signal, and
set the operation mode of the clock lane to the high-speed mode based on a result of the determining regardless of the operation of the mode of the clock lane.

### Claim 16 (depends on 15)

The transmission system of claim 15, wherein the clock lane control circuit is configured to generate an interrupt signal in response to the state signal.

### Claim 17 (depends on 16)

The transmission system of claim 16, wherein the clock lane control circuit comprises a clock lane finite state machine (FSM) configured to control the operation mode of the clock lane,
wherein the data lane control circuit comprises a data lane FSM for controlling the operation mode of the data lane,
wherein the data lane FSM is configured to:
monitor a level of the data signal, generate a state signal indicating the operation mode of the data lane based on a result of the monitoring, and output the generated state signal to the clock lane FSM, and
wherein the clock lane FSM is configured to:
set the operation mode of the clock lane to the high-speed mode in response to the state signal.

### Claim 18 (depends on 15)

The transmission system of claim 15, wherein the clock lane control circuit is configured to:
detect that the operation mode of the data lane is switched from the low-power mode to the high-speed mode,
generate an interrupt signal according to a result of the detection, and
set the operation mode of the clock lane to the high-speed mode in response to the generated interrupt signal.

### Claim 19 (depends on 16)

The transmission system of claim 16, wherein the clock lane control circuit comprises a noise sensing circuit configured to detect external noise occurring on the clock lane, and the clock lane control circuit is further configured to:
determine whether the operation mode of the data lane is switched from the low-power mode to the high-speed mode, when the external noise is detected by the noise sensing circuit, and
set the operation mode of the clock lane to the high-speed mode, when the operation mode of the data lane is switched from the low-power mode to the high-speed mode.

### Claim 20

A transmission system comprising:
an interface comprising:
a transmission apparatus; and
a reception apparatus; and
a clock lane and one or more data lanes configured to operate in one of a first mode and a second mode;
wherein the reception apparatus comprises a clock lane control circuit comprising a noise sensing circuit configured to detect external noise occurring on the clock lane, and
wherein the clock lane control circuit is configured to:
determine whether an operation mode of the one or more data lanes has been switched from the first mode to the second mode, when the external noise is detected by the noise sensing circuit, and
set the operation mode of the clock lane to the second mode when the operation mode of the one or more data lanes is switched from the first mode to the second mode regardless of the operation mode of the clock lane.

### Claim 21 (depends on 20)

The system of claim 20, wherein the first mode is a low-power mode and the second mode is a high-speed mode.