# US 11,112,816 B2 · Miniaturized digital temperature sensor

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- Number: US 11,112,816 B2
- Document ID: US11112816B2
- Status: Granted
- Kind: B2
- Application number: 15/959,239
- Filed: 2018-04-22
- Published: 2019-10-24
- Granted: 2021-09-07
- Earliest claimed: 2018-04-22
- Assignees: Birad—Research & Development Company Ltd.
- Applicants: Birad—Research & Development Company Ltd.
- Inventors: Ori Bass; Joseph Shor
- Web page: https://patentgrep.com/patent/US11112816B2

## CPC

- G05F 3/30: Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities (G05F3/26 takes precedence)
- G01K 7/01: using semiconducting elements having PN junctions (G01K7/02, G01K7/16, G01K7/30 take precedence)
- G01K 7/015: {using microstructures, e.g. made of silicon}
- G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G01K: MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR (radiation pyrometry G01J5/00)

## Abstract

A sensor circuit includes a bandgap reference circuit (BGREF) that produces two outputs, a temperature dependent output and a reference voltage, which does not change with temperature. The temperature dependent output includes a PTAT (proportional to absolute temperature, rising with increased temperature) portion and a CTAT (complementary to absolute temperature, falling with increased temperature) portion. Circuitry is provided that calculates the reference voltage by adding the PTAT portion and a divided version of the CTAT portion in which the CTAT portion has been divided by a divisor.

## Claims

### Claim 1

A temperature sensor circuit comprising:
two temperature dependent voltages, one of which is a PTAT voltage, which is proportional to absolute temperature, rising with increased temperature, and another of which is a CTAT voltage, which is complementary to absolute temperature, falling with increased temperature; and
circuitry that calculates the temperature by adding said PTAT voltage and a divided version of said CTAT voltage in which said CTAT voltage has been divided by a divisor, wherein said CTAT voltage comprises Vbe (base-emitter voltage) and said PTAT voltage comprises dVbe, and the Vbe and dVbe voltages are generated by a single bipolar junction transistor (BJT).

### Claim 2 (depends on 1)

The sensor circuit according to claim 1, wherein said circuitry that calculates said temperature by adding said PTAT voltage and the divided version of said CTAT voltage in which said CTAT voltage has been divided by a divisor is defined by an equation:
D
⁢
⁢
T
⁢
⁢
R
=
Δ
⁢
⁢
vbe
Δ
⁢
⁢
vbe
+
vbe
⁢
β
α
wherein DTR is a digital temperature reading of said temperature, Δvbe is the dVbe voltage, vbe is the Vbe voltage, and α and β are coefficients of two different states of a programmable integrator transfer function unit that comprises a feedback signal that determines which of said two different states are used by said programmable integrator transfer function unit.

### Claim 3 (depends on 2)

The sensor according to claim 2, wherein the Vbe voltage is coupled via a first switch to a first integrator (g1) whose multiplication factor or gain is β and the Δvbe voltage is coupled via a second switch to a second integrator (g2) whose multiplication factor or gain is a.

### Claim 4 (depends on 3)

The sensor circuit according to claim 3, wherein said BJT has a collector coupled to ground, a base coupled to ground and an emitter coupled via a node (n0) to a first switch, with a clock phase (s2), and to a second switch, with a clock phase (s1), said first switch being coupled to a drain of a first PMOS transistor, which is a branch of unity multiplication, a gate of said first PMOS transistor being coupled to an input (Pbias1) and a source of said first PMOS transistor being coupled to Vcc, a gate of said first PMOS transistor being coupled to a gate of a second PMOS transistor, which is a branch of n multiplication, said second switch being coupled to a drain of said second PMOS transistor, a source of said second PMOS transistor being coupled to Vcc, bulks of said first and second transistors both being coupled to Vcc; and
wherein said BJT serves as a parasitic diode, and said first and second PMOS transistors serve as two current sources which alternate as needed or instructed from a charge sharing circuit such that when said first switch is conducting, a Vbe1 voltage is produced and when said second switch is conducting a Vben voltage is produced, wherein the Vbe1 and Vben voltages are used to generate the Vbe and dVbe voltages.

### Claim 5 (depends on 4)

The sensor circuit according to claim 4, wherein said node (n0) is coupled to a node (31) and from there to a third switch with a clock phase (FB) which is coupled to a fourth switch with a clock phase (s2), which in turn is coupled to a node (32), and wherein said node (31) is coupled via a node (33) to two switched capacitor branches, wherein in one of said branches, said node (33) is coupled to a fifth switch with a clock phase (s1), which in turn is coupled via said node (32) to a capacitor (C2), and in the other of said branches, said node (33) is coupled to a sixth switch with a clock phase (s1), which in turn is coupled via a node (34) to a capacitor (C1), said node (33) being coupled to a seventh switch with a clock phase (FB) which is coupled via a node (35) to an eighth switch with a clock phase (FB_n), and a ninth switch with a clock phase (s2) is coupled to said nodes (34) and (35), and said capacitor (C2) is coupled to a node (36) and said capacitor (C1) is coupled to a node (37), a capacitor (C3) is coupled between said node (36) and a node (38), and a tenth switch with a clock phase (FB_n) is coupled between said node (38) and a node (39), and a capacitor (C4) is coupled between said nodes (36) and (39), and an amplifier (A1) is coupled between a node (70) at an input of said amplifier (A1) and said node (39) at an output of said amplifier (A1), an eleventh switch with a clock phase (s2) is coupled between said nodes (38) and (70), an inverting amplifier (i1) is coupled between said node (37) and a node (71), and a twelfth switch with a clock phase (s1) is coupled between said nodes (37) and (71), and a thirteenth switch with a clock phase (s2) is coupled between said nodes (70) and (71), and an amplifier (A2) is coupled to said node (71) and outputs to a Flip-Flop (C), which is coupled to an inverter (i2) which is coupled to the clock phase (FB) and via another inverter (i3) to the clock phase (FB_n), wherein said Flip-flop (C) receives (S2) at its clock input and the output of amplifier (A2) at its data input.

### Claim 6 (depends on 3)

The sensor according to claim 3, wherein a first capacitor (C1) and a second capacitor (C2) transfer the Vbe and dVbe into said programmable integrator transfer function unit, and a third capacitor (C3) and a fourth capacitor (C4) determine a multiplication factor of said programmable integrator transfer function unit, and said first integrator
ℊ1
=
β
=
C
⁢
1
(
C
⁢
3
+
C
⁢
4
)
and said second integrator
ℊ2
=
α
=
C
⁢
1
+
C
⁢
2
C
⁢
3
.

### Claim 7 (depends on 1)

The sensor circuit according to claim 1, wherein circuitry that divides said CTAT voltage by the divisor comprises capacitors and said divisor is a function of capacitances of said capacitors.