# US 11,112,659 B2 · Array substrate and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,112,659 B2 - Document ID: US11112659B2 - Status: Granted - Kind: B2 - Application number: 16/474,527 - Filed: 2018-06-28 - Published: 2019-11-28 - Granted: 2021-09-07 - Earliest claimed: 2017-08-31 - Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd. - Applicants: Hefei Xinsheng Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd. - Inventors: Guohua Wang; Wenming Ren; Fei Gao - Web page: https://patentgrep.com/patent/US11112659B2 ## CPC - G02F 1/136204: {Arrangements to prevent high voltage or static electricity failures} - G02F 1/136286: {Wiring, e.g. gate line, drain line} - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/60: wherein the TFTs are in active matrices - H10D 89/911: {using passive elements as protective elements} - H10D 89/931: {characterised by the dispositions of the protective arrangements} - G02F 1/133784: {by rubbing} - G02F 1/1345: Conductors connecting electrodes to cell terminals - G02F 2202/22: Antistatic materials or arrangements - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract An array substrate includes a display region and a wiring region. The wiring region includes a plurality of sets of signal line leads and a plurality of wiring regions, and a same set of signal line leads extends to a same bonding region disposed in the wiring region. The wiring region further includes at least one auxiliary wiring structure. Each auxiliary wiring structure is disposed between adjacent two sets of signal line leads and includes a peripheral closed wiring loop. Each peripheral closed wiring loop includes a plurality of corner portion, and a shape of at least one corner portion proximate to the display region is a curve. ## Claims ### Claim 1 An array substrate, comprising a display region and a wiring region, wherein the wiring region includes a plurality of sets of signal line leads, and a same set of signal line leads extends to a corresponding bonding region disposed in the wiring region; the wiring region further includes auxiliary wiring structure(s) each disposed between adjacent two sets of signal line leads; each auxiliary wiring structure includes a peripheral closed wiring loop; the peripheral closed wiring loop includes at least one corner portion; a shape of all of the at least one corner portion of the peripheral closed wiring loop is a curved shape; the peripheral closed wiring loop includes at least three peripheral wires sequentially coupled; and each auxiliary wiring structure further includes interior wires disposed inside the peripheral closed wiring loop, and the peripheral closed wiring loop is provided with at least one tip facing the interior wires. ### Claim 2 (depends on 1) The array substrate according to claim 1, wherein the at least three peripheral wires of the peripheral closed wiring loop include a first peripheral wire proximate to the display region of the array substrate; and the first peripheral wire is provided with the at least one tip. ### Claim 3 (depends on 2) The array substrate according to claim 2, wherein the first peripheral wire is parallel to an arrangement direction of bonding regions. ### Claim 4 (depends on 3) The array substrate according to claim 3, wherein the at least three peripheral wires of the peripheral closed wiring loop are four peripheral wires; the four peripheral wires include a second peripheral wire disposed parallel to the first peripheral wire, and a third peripheral wire and a fourth peripheral wire disposed on two sides of the first peripheral wire and the second peripheral wire, and the third peripheral wire and the fourth peripheral wire are disposed opposite to each other; and the third peripheral wire is disposed parallel to a signal line lead of a set of signal line leads closest to the auxiliary wiring structure, the fourth peripheral wire is disposed parallel to a signal line lead of another set of signal line leads closest to the auxiliary wiring structure, and the two sets of signal line leads are proximate to each other. ### Claim 5 (depends on 4) The array substrate according to claim 4, wherein in the at least one peripheral closed wiring loop, a length of the first peripheral wire is less than a length of the second peripheral wire. ### Claim 6 (depends on 1) The array substrate according to claim 1, wherein the interior wires include at least one first interior wire; each first interior wire includes second interior sub-wire(s) directly connected to the peripheral closed wiring loop, and a first interior sub-wire disconnected from each second interior sub-wire; and the first interior sub-wire is disposed parallel to the first peripheral wire, and the first interior sub-wire is disposed at least directly opposite to at least a portion of the first peripheral wire where the at least one tip is disposed; and each first interior wire further includes at least one conductive connecting portion; in each first interior wire, the first interior sub-wire and a second interior sub-wire proximate to the first interior sub-wire are coupled through one conductive connecting portion. ### Claim 7 (depends on 6) The array substrate according to claim 6, wherein the first interior sub-wire of the first interior wire is disposed proximate to the first peripheral wire. ### Claim 8 (depends on 6) The array substrate according to claim 6, wherein the at least one first interior wire includes at least two second interior sub-wires, and in the first interior wire, one end of the first interior sub-wire is coupled to one second interior sub-wire through a conductive connecting portion, and another end of the first interior sub-wire is coupled to another second interior sub-wire through another conductive connecting portion. ### Claim 9 (depends on 6) The array substrate according to claim 6, wherein the at least one conductive connecting portion is mainly made of a transparent conductive material. ### Claim 10 (depends on 6) The array substrate according to claim 6, wherein a resistivity of at least one of the at least one conductive connecting portion is greater than a resistivity of the first interior wire. ### Claim 11 (depends on 1) A display device, comprising the array substrate according to claim 1. ### Claim 12 (depends on 1) The array substrate according to claim 1, wherein each tip is a protruding structure disposed on the peripheral closed wiring loop. ### Claim 13 An array substrate, comprising a display region and a wiring region, wherein the wiring region includes a plurality of sets of signal line leads, and a same set of signal line leads extends to a corresponding bonding region disposed in the wiring region; the wiring region further includes auxiliary wiring structure(s) each disposed between adjacent two sets of signal line leads; each auxiliary wiring structure includes a peripheral closed wiring loop; the peripheral closed wiring loop includes at least one corner portion; a shape of all of the at least one corner portion of the peripheral closed wiring loop is a curved shape; the peripheral closed wiring loop includes at least three peripheral wires sequentially coupled; and each auxiliary wiring structure further includes interior wires disposed inside the peripheral closed wiring loop, and the peripheral closed wiring loop includes at least one tip facing the interior wires. ### Claim 14 (depends on 13) The array substrate according to claim 13, wherein the at least three peripheral wires of the peripheral closed wiring loop include a first peripheral wire proximate to the display region of the array substrate; and the first peripheral wire includes the at least one tip. ### Claim 15 (depends on 13) The array substrate according to claim 13, wherein the interior wires include at least one first interior wire; each first interior wire includes second interior sub-wire(s) directly connected to the peripheral closed wiring loop, and a first interior sub-wire disconnected from each second interior sub-wire; and the first interior sub-wire is disposed parallel to the first peripheral wire, and the first interior sub-wire is disposed at least directly opposite to at least a tip of the first peripheral wire; and each first interior wire further includes at least one conductive connecting portion; in each first interior wire, the first interior sub-wire and a second interior sub-wire proximate to the first interior sub-wire are coupled through one conductive connecting portion. ### Claim 16 (depends on 13) The array substrate according to claim 13, wherein each tip is a bent structure of the peripheral closed wiring loop. ### Claim 17 (depends on 13) A display device, comprising the array substrate according to claim 13.