# US 11,112,570 B2 · Fabrication method of high aspect ratio solder bumping with stud bump and injection molded solder, and flip chip joining with the solder bump

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,112,570 B2
- Document ID: US11112570B2
- Status: Granted
- Kind: B2
- Application number: 16/744,958
- Filed: 2020-01-16
- Published: 2020-05-14
- Granted: 2021-09-07
- Earliest claimed: 2017-11-02
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Toyohiro Aoki; Takashi Hisada; Eiji Nakamura; Masao Tokunari
- Web page: https://patentgrep.com/patent/US11112570B2

## CPC

- G02B 6/4232: {using the surface tension of fluid solder to align the elements, e.g. solder bump techniques (flip-chip mounting techniques in assembly of semiconductor devices H10W72/072)}
- G02B 6/12002: {Three-dimensional structures}
- G02B 6/1221: {made from organic materials}
- G02B 6/13: Integrated optical circuits characterised by the manufacturing method
- G02B 6/4214: {the intermediate optical element having redirecting reflective means, e.g. mirrors, prisms for deflecting the radiation from horizontal to down- or upward direction toward a device (G02B6/4246 takes precedence)}
- H10P 76/00: Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
- G02B 2006/12069: {Organic material}
- G02B 2006/12123: {Diode}
- H10F 77/413: {directly associated or integrated with the devices, e.g. back reflectors (directly associated or integrated with photovoltaic cells H10F77/42)}
- H10F 77/933: {for devices having potential barriers}
- H10H 20/0364: {of interconnections}
- H10H 20/855: Optical field-shaping means, e.g. lenses
- H10H 20/857: Interconnections, e.g. lead-frames, bond wires or solder balls
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01204: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/01212: {at a different location than on the final device, e.g. forming solder preforms}
- H10W 72/01223: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/01233: {in liquid form, e.g. spin coating, spray coating or immersion coating}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01251: {Changing the shapes of bumps}
- H10W 72/01255: {by using masks}
- H10W 72/01257: {by reflowing}
- H10W 72/01271: {Cleaning, e.g. oxide removal or de-smearing}
- H10W 72/01953: {by etching}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07253: {changes in shapes}
- H10W 72/223: {characterised by the structure of the outermost layers, e.g. multilayered coatings}
- H10W 72/224: {Bumps having multiple side-by-side cores}
- H10W 72/225: {Bumps having a filler embedded in a matrix}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/245: {of outermost layers of multilayered bumps, e.g. bump coating being only on a part of a bump core}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/253: {not comprising solid metals or solid metalloids, e.g. polymers or ceramics}
- H10W 72/255: {of outermost layers of multilayered bumps, e.g. material of a coating}
- H10W 72/287: {Flow barriers}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- G02B: OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A technique for fabricating bumps on a substrate is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared. A bump base is formed on each pad of the substrate. Each bump base has a tip extending outwardly from the corresponding pad. A resist layer is patterned on the substrate to have a set of holes through the resist layer. Each hole is aligned with the corresponding pad and having space configured to surround the tip of the bump base formed on the corresponding pad. The set of the holes in the resist layer is filled with conductive material to form a set of bumps on the substrate. The resist layer is stripped from the substrate with leaving the set of the bumps.

## Claims

### Claim 1

A method for fabricating bumps on a substrate, the method comprising:
forming a bump base on each pad of a set of pads on a substrate, each bump base having a body and a tip extending outwardly from the corresponding pad;
patterning a resist layer on the substrate to have a set of holes through the resist layer, each hole being aligned with the corresponding pad and having space configured to surround the tip of the bump base formed on the corresponding pad; and
filling the set of the holes with conductive material to form a set of bumps on the substrate.

### Claim 2 (depends on 1)

The method of claim 1, wherein the conductive material is solder material and injected into each hole in a molten state and the set of the bumps is a set of solder capped bumps each being made of material of the bump base formed on the substrate and the solder material filled into the hole.

### Claim 3 (depends on 1)

The method of claim 1, wherein each bump base extends the tip in a direction approximately normal to the surface of the substrate, and the resist layer has a thickness aligned to the levels of the tips of the bump bases.

### Claim 4 (depends on 1)

The method of claim 1, wherein each bump base is a stud bump formed by wire bonding.

### Claim 5 (depends on 4)

The method of claim 4, wherein each stud bump is selected from the group consisting of an Au stud bump, a bare Cu stud bump, a Pd-coated Cu stud bump and an Ag stud bump.

### Claim 6 (depends on 4)

The method of claim 4, wherein each stud bump is a Cu stud bump having a protection layer formed on a surface thereof.

### Claim 7 (depends on 4)

The method of claim 4, further comprising:
flattening the tips of the stud bumps by coining.

### Claim 8 (depends on 1)

The method of claim 1, wherein patterning the resist layer on the substrate comprises:
applying a photoresist material on the substrate; and
exposing and developing the photoresist material so as to open holes through the photoresist material with aligning with the pads, the photoresist material having the holes corresponding to the resist layer having the set of the holes.

### Claim 9 (depends on 1)

A method for interconnecting a semiconductor device with external circuitry by bumps, the method comprising:
performing the method of claim 1 to prepare a semiconductor device including at least a part of the bumps formed on the surface of the substrate; and
preparing external circuitry having a set of electrodes formed on a surface thereof;
mounting the semiconductor device to the external circuitry such that the bumps of the semiconductor device are in contact with the electrodes of the external circuitry, respectively.

### Claim 10 (depends on 9)

The method of claim 9, wherein the bumps of the semiconductor device includes a set of solder capped bumps each being made of material of the bump base and solder material.

### Claim 11 (depends on 9)

The method of claim 9, wherein the external circuitry has a layer having a set of via holes aligned with the electrodes, the bumps of the semiconductor device are inserted into the via holes of the external circuitry, respectively, when mounting the semiconductor device to the external circuitry.

### Claim 12 (depends on 11)

The method of claim 11, wherein the external circuitry is provided as a form of an organic substrate having an optical waveguide integrated thereon as the layer having the set of via holes.

### Claim 13 (depends on 9)

The method of claim 9, wherein the semiconductor device is mounted to the external circuitry without forming a pre-solder on each electrode of the external circuitry.

### Claim 14

A structure comprising:
a substrate including a set of pads formed on a surface thereof; and
a set of bumps formed on the pads, each bump being fabricated by:
forming a bump base on each pad, each bump base having a tip extending outwardly from the corresponding pad; and
filling conductive material into a set of holes of a resist layer patterned on the substrate.

### Claim 15 (depends on 14)

The structure of claim 14, wherein the conductive material is solder material and solidified in each hole and the set of the bumps is a set of solder capped bumps each being made of the material of the bump base formed on the substrate and the solder material filled into the hole.

### Claim 16 (depends on 14)

The structure of claim 14, further comprising:
a semiconductor device interconnected with external circuitry by bumps,
wherein the external circuitry includes a set of electrodes formed on a surface thereof, and
wherein the semiconductor device is mounted to the external circuitry such that the bumps of the semiconductor device are in contact with the electrodes of the external circuitry, respectively.

### Claim 17 (depends on 16)

The structure of claim 16, wherein the bumps of the semiconductor device includes a set of solder capped bumps each being made of material of the bump base and solder material.

### Claim 18 (depends on 16)

The structure of claim 16, wherein the external circuitry has a layer having a set of via holes aligned with the electrodes, the bumps of the semiconductor device are inserted into the via holes of the external circuitry, respectively, when mounting the semiconductor device to the external circuitry.

### Claim 19 (depends on 18)

The structure of claim 18, wherein the external circuitry is provided as a form of an organic substrate having an optical waveguide integrated thereon as the layer having the set of via holes.

### Claim 20 (depends on 16)

The structure of claim 16, wherein the semiconductor device is mounted to the external circuitry without a pre-solder formed on each electrode of the external circuitry.