Built-in self-test circuits and related methods
AssigneeTexas Instruments Incorporated
InventorJacco van Oevelen
Life of this patent
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Abstract
Built-in self-test (BIST) circuits and related methods are disclosed. An example BIST circuit includes a state machine to generate a control signal to reduce a gate voltage associated with a transistor from a first voltage to a second voltage when an enable signal is asserted, the transistor to be enabled at the first voltage and the second voltage, and assert an alert signal when a gate-to-source voltage associated with the transistor satisfies a threshold when the gate voltage is reduced to the second voltage.
Claims20
A built-in self-test (BIST) circuit, comprising:
- a state machine having an enable input, having an alert output, having a gate voltage control output adapted to be coupled to a gate of a power transistor, and having a source voltage input adapted to be coupled to the source of the power transistor, the state machine having states to:
- generate a gate control signal on the gate voltage control output to reduce a gate voltage associated with the power transistor from a first voltage to a second voltage when an enable signal is asserted on the enable input, the power transistor to be enabled at the first voltage and the second voltage;
- and
- assert an alert signal on the alert output when a gate-to-source voltage associated with the power transistor satisfies a threshold when the gate voltage is reduced to the second voltage.
A power conversion system, comprising:
- a power conversion stage;
- a power transistor having a drain, a gate, and a source and being coupled to the power conversion stage;
- and
- a built-in self-test (BIST) circuit, the BIST circuit including a state machine having an enable input, having an alert output, having a gate voltage control output coupled to the gate of the power transistor, and having a source voltage input coupled to the source of the power transistor, the state machine having states to:
- generate a gate control signal to reduce a gate voltage associated with the power transistor from a first voltage to a second voltage when an enable signal on the enable input is asserted, the power transistor to be enabled at the first voltage and the second voltage;
- and
- assert an alert signal on the alert output when a gate-to-source voltage associated with the power transistor satisfies a threshold when the gate voltage is reduced to the second voltage.
A gate-driver circuit, comprising:
- a state machine having an enable input, having an alert output, having a gate voltage control output adapted to be coupled to a gate of a power transistor, and having a source voltage input adapted to be coupled to a source of the power transistor;
- a variable voltage supply, the variable voltage supply coupled to the gate voltage control output, a first terminal of the variable voltage supply adapted to be coupled to a drain of the power transistor;
- an amplifier, a first input of the amplifier coupled to a second terminal of the variable voltage supply, an output of the amplifier to be coupled to the gate of the power transistor, a second input of the amplifier to be coupled to the source of the power transistor;
- and
- a comparator, an output of the comparator coupled to the source voltage input, a first input of the comparator coupled to the output of the amplifier, the first input of the comparator to be coupled to the gate of the power transistor, a second input of the comparator to be coupled to the source of the power transistor.
Dependencies are inferred from the claim text.