# US 11,112,453 B2 · Self testing fault circuit apparatus and method

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- Number: US 11,112,453 B2
- Document ID: US11112453B2
- Status: Granted
- Kind: B2
- Application number: 16/875,263
- Filed: 2020-05-15
- Published: 2020-09-03
- Granted: 2021-09-07
- Earliest claimed: 2008-01-29
- Assignees: Leviton Manufacturing Co., Inc.
- Applicants: Leviton Manufacturing Company, Inc.
- Inventors: Michael Ostrovsky; Adam Kevelos
- Web page: https://patentgrep.com/patent/US11112453B2

## CPC

- G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)}
- G01R 31/3277: {of low voltage devices, e.g. domestic or industrial devices, such as motor protections, relays, rotation switches}
- H02H 3/335: {the main function being self testing of the device}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)

## Abstract

A process for self testing a fault circuit includes disabling an actuator, performing a self-test by creating a simulated fault signal across at least a portion of a half cycle of a first polarity and across at least a portion of a half cycle of a second polarity, and determining whether the self-test was successful.

## Claims

### Claim 1

A self-testing fault circuit interrupter device comprising:
a) a fault circuit comprising:
i) a line monitoring circuit;
ii) a line interrupting circuit comprising contacts; and
iii) a fault detector circuit which is configured to selectively operate the line interrupting circuit when a fault is detected from the line monitoring circuit;
b) a self-test circuit including a microcontroller, the self-test circuit configured to conduct a self-test on the fault circuit;
c) a timing circuit configured to control a duration of an output of the fault detector circuit.

### Claim 2 (depends on 1)

The device of claim 1, wherein the self-test circuit further comprises:
a transistor coupled to an output of the microcontroller.

### Claim 3 (depends on 1)

The device of claim 1, wherein the fault detector circuit comprises an integrated circuit.

### Claim 4 (depends on 1)

The device of claim 1, wherein the fault detector circuit further comprises:
a capacitor,
wherein the timing circuit is further configured to control a discharge rate of the capacitor.

### Claim 5 (depends on 1)

The device of claim 1, wherein the fault detector circuit is an integrating fault detector circuit.

### Claim 6 (depends on 4)

The device of claim 4, wherein the timing circuit comprises:
a transistor configured to selectively increase the discharge rate of the capacitor.

### Claim 7 (depends on 4)

The device of claim 4, wherein the timing circuit comprises:
a resistor, wherein a resistance level of the resistor controls the discharge rate of the capacitor.

### Claim 8 (depends on 4)

The device of claim 4, wherein the timing circuit is controlled by the microcontroller.

### Claim 9 (depends on 1)

The device of claim 1, further comprising:
a zero crossing circuitry in communication with the microcontroller, wherein the microcontroller in combination with the zero crossing circuitry forms the line monitoring circuit which is configured to sense an output of the zero crossing circuitry to determine an over voltage condition or an under voltage condition.

### Claim 10 (depends on 1)

The device of claim 1, wherein the self-test circuit is further configured to provide a simulated fault signal during at least a portion of a first half cycle and during at least a portion of a second half cycle of opposite polarity.

### Claim 11 (depends on 1)

The device of claim 1, wherein the fault detector circuit comprises:
an integrated circuit, wherein the microcontroller is further configured to conduct the self-test during at least a portion of a positive half cycle and during at least a portion of a negative half cycle of AC current.

### Claim 12 (depends on 1)

The device of claim 1, wherein the line monitoring circuit comprises a sensor.

### Claim 13 (depends on 1)

The device of claim 1, further comprising:
a line side coupled to building wiring, providing power to the device;
a load side coupled to a downstream load; and
a plurality of selectively separable contacts configured to electrically connect/disconnect the line side from the load side,
wherein the microcontroller is configured to actuate the line interrupting circuit.

### Claim 14 (depends on 9)

The device of claim 9, wherein a level of the over voltage or under voltage is determined based on a slope of a zero crossing output.

### Claim 15 (depends on 14)

The device of claim 14, wherein the microcontroller upon determining an over voltage or under voltage condition is configured to perform one or more following tasks: indicate an over voltage or under voltage condition and actuate the line interrupting circuit.

### Claim 16 (depends on 1)

The device of claim 1, wherein the timing circuit is further configured to control a time period of the self-test, and to shorten the time period for the self-test in presence of an actual fault.

### Claim 17 (depends on 1)

The device of claim 1, wherein the line interrupting circuit is selectively activated by the self-test circuit when the self-test circuit determines there is a failed self-test condition.

### Claim 18

A self-testing fault circuit interrupter device comprising:
a) a fault circuit comprising:
i) a line monitoring circuit;
ii) a line interrupting circuit; and
iii) a fault detector circuit which is configured to selectively operate the line interrupting circuit when a fault is detected from the line monitoring circuit;
b) a self-test circuit configured to conduct a self-test on the fault circuit;
c) a timing circuit configured to control a duration of an output of the fault detector circuit.

### Claim 19 (depends on 18)

The device of claim 18, wherein the fault detector circuit comprises an integrated circuit.

### Claim 20 (depends on 18)

The device of claim 18, wherein the fault detector circuit further comprises:
a capacitor,
wherein the timing circuit is further configured to control a discharge rate of the capacitor.

### Claim 21 (depends on 20)

The device of claim 20, wherein the timing circuit comprises:
a transistor configured to selectively increase the discharge rate of the capacitor.

### Claim 22 (depends on 20)

The device of claim 20, wherein the timing circuit comprises:
a resistor, wherein a resistance level of the resistor controls the discharge rate of the capacitor.

### Claim 23 (depends on 18)

The device of claim 18, wherein the timing circuit is controlled by a microcontroller.

### Claim 24 (depends on 18)

The device of claim 18, further comprising:
a microcontroller; and
a zero crossing circuitry in communication with the microcontroller, wherein the microcontroller in combination with the zero crossing circuitry forms the line monitoring circuit which is configured to sense an output of the zero crossing circuitry to determine an over voltage condition or an under voltage condition.

### Claim 25 (depends on 24)

The device of claim 24, wherein a level of the over voltage condition or under voltage condition is determined based on a slope of a zero crossing output.

### Claim 26 (depends on 18)

The device of claim 18, wherein the fault detector circuit is an integrating fault detector circuit.

### Claim 27 (depends on 18)

The device of claim 18, wherein the self-test circuit is further configured to provide a simulated fault signal during at least a portion of a first half cycle and during at least a portion of a second half cycle of opposite polarity.

### Claim 28 (depends on 18)

The device of claim 18, wherein the fault detector circuit comprises:
an integrated circuit, wherein the self-test circuit is further configured to conduct the self-test during at least a portion of a positive half cycle and during at least a portion of a negative half cycle of AC current.

### Claim 29 (depends on 18)

The device of claim 18, wherein the line monitoring circuit comprises a sensor.

### Claim 30 (depends on 18)

The device of claim 18, further comprising:
a line side coupled to building wiring, providing power to the device;
a load side coupled to a downstream load; and
a plurality of selectively separable contacts configured to electrically connect/disconnect the line side from the load side.

### Claim 31 (depends on 18)

The device of claim 18, wherein upon determining an over voltage or under voltage condition, the self-test circuit is configured to indicate an over voltage or under voltage condition or actuate the line interrupting circuit.

### Claim 32 (depends on 18)

The device of claim 18, wherein the timing circuit is further configured to control a time period of the self-test, and to shorten the time period for the self-test in presence of an actual fault.

### Claim 33 (depends on 18)

The device of claim 18, wherein the line interrupting circuit is selectively activated by the self-test circuit when the self-test circuit determines there is a failed self-test condition.

### Claim 34

A self-testing fault circuit interrupter device comprising:
a) a fault circuit comprising:
i) a line monitoring circuit;
ii) a line interrupting circuit; and
iii) a fault detector circuit which is configured to selectively operate the line interrupting circuit when a fault is detected from the line monitoring circuit;
b) a self-test circuit configured to conduct a self-test on the fault circuit, the self-test circuit configured to selectively operate the line interrupting circuit;
c) a timing circuit configured to control a duration of an output of the fault detector circuit.

### Claim 35 (depends on 34)

The device of claim 34, wherein the fault detector circuit comprises an integrated circuit.

### Claim 36 (depends on 34)

The device of claim 34, wherein the fault detector circuit further comprises:
a capacitor,
wherein the timing circuit is further configured to control a discharge rate of the capacitor.

### Claim 37 (depends on 36)

The device of claim 36, wherein the timing circuit comprises:
a transistor configured to selectively increase the discharge rate of the capacitor.

### Claim 38 (depends on 36)

The device of claim 36, wherein the timing circuit comprises:
a resistor, wherein a resistance level of the resistor controls the discharge rate of the capacitor.

### Claim 39 (depends on 34)

The device of claim 34, wherein the timing circuit is controlled by a microcontroller.

### Claim 40 (depends on 34)

The device of claim 34, further comprising:
a microcontroller; and
a zero crossing circuitry in communication with the microcontroller, wherein the microcontroller in combination with the zero crossing circuitry forms the line monitoring circuit which is configured to sense an output of the zero crossing circuitry to determine an over voltage condition or an under voltage condition.

### Claim 41 (depends on 10)

The device of claim 10, wherein a level of the over voltage condition or under voltage condition is determined based on a slope of a zero crossing output.

### Claim 42 (depends on 34)

The device of claim 34, wherein the fault detector circuit is an integrating fault detector circuit.

### Claim 43 (depends on 34)

The device of claim 34, wherein the self-test circuit is further configured to provide a simulated fault signal during at least a portion of a first half cycle and during at least a portion of a second half cycle of opposite polarity.

### Claim 44 (depends on 34)

The device of claim 34, wherein the fault detector circuit comprises:
an integrated circuit, wherein the self-test circuit is further configured to conduct the self-test during at least a portion of a positive half cycle and during at least a portion of a negative half cycle of AC current.

### Claim 45 (depends on 34)

The device of claim 34, wherein the line monitoring circuit comprises a sensor.

### Claim 46 (depends on 34)

The device of claim 34, wherein upon determining an over voltage or under voltage condition, the self-test circuit is configured to indicate an over voltage or under voltage condition or actuate the line interrupting circuit.