# US 11,112,436 B2 · Spark gap structures for detection and protection against electrical overstress events > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,112,436 B2 - Document ID: US11112436B2 - Status: Granted - Kind: B2 - Application number: 16/360,356 - Filed: 2019-03-21 - Published: 2019-09-26 - Granted: 2021-09-07 - Earliest claimed: 2018-03-26 - Assignees: Analog Devices International Unlimited Company - Applicants: Analog Devices International Unlimited Company - Inventors: David J. Clarke; Stephen Denis Heffernan; Nijun Wei; Alan J. O'Donnell; Patrick Martin McGuinness; Shaun Bradley; Edward John Coyne; David Aherne; David M. Boland - Web page: https://patentgrep.com/patent/US11112436B2 ## CPC - G01R 19/16504: {characterised by the components employed} - G01R 19/165: Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values - G01R 31/002: {where the device under test is an electronic circuit} - G01R 31/2832: {Specific tests of electronic circuits not provided for elsewhere (G01R31/2801, G01R31/316 take precedence)} - G01R 31/2856: {Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]} - G01R 31/2879: {related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads} - G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)} - H02H 9/00: Emergency protective circuit arrangements for limiting excess current or voltage without disconnection - H02H 9/041: {using a short-circuiting device} - H02H 9/042: {comprising means to limit the absorbed power or indicate damaged over-voltage protection device} - H02H 9/044: {Physical layout, materials not provided for elsewhere (varistors H01C7/12; spark-gaps H01T; Ovshinsky devices H10N70/00)} - H10D 89/911: {using passive elements as protective elements} - H10W 20/493: {Fuses, i.e. interconnections changeable from conductive to non-conductive} - H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) - H10W 42/80: protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, an electrical overstress monitor and/or protection device includes a two different conductive structures configured to electrically arc in response to an EOS event and a sensing circuit configured to detect a change in a physical property of the two conductive structures caused by the EOS event. The two conductive structures have facing surfaces that have different shapes. ## Claims ### Claim 1 An electrical overstress (EOS) monitor/protection device, comprising: two different conductive structures separated by a gap therebetween and configured to electrically arc in response to an EOS event, wherein the two conductive structures are lithographically defined using a semiconductor fabrication technology, and wherein arcing surfaces of the two conductive structures that face each other have different shapes; and a sensing circuit configured to detect a change in physical property of the EOS monitor/protection device caused by the EOS event. ### Claim 2 (depends on 1) The EOS monitor/protection device of claim 1, wherein one but not the other of the two conductive structures comprises one or more tips protruding towards the other of the two conductive structures. ### Claim 3 (depends on 1) The EOS monitor/protection device of claim 1, wherein one of the two conductive structures comprises a substantially straight edge facing the other of the two conductive structures. ### Claim 4 (depends on 3) The EOS monitor/protection device of claim 3, wherein the one of the two conductive structures comprises a conductive line extending in a direction orthogonal to a direction of separation of the two conductive structures. ### Claim 5 (depends on 4) The EOS monitor/protection device of claim 4, wherein the conductive line is configured to be reduced in width upon passing current therethrough, thereby increasing a distance of the gap. ### Claim 6 (depends on 1) The EOS monitor/protection device of claim 1, wherein one of the two conductive structures at least partly laterally surrounds the other of the two conductive structures. ### Claim 7 (depends on 1) The EOS monitor/protection device of claim 1, wherein one or both of the two conductive structures are configured to be positionally displaced relative to one another post-fabrication such that a distance of the gap is tunable. ### Claim 8 (depends on 1) The EOS monitor/protection device of claim 1, wherein the gap comprises an arcing medium comprising a solid dielectric. ### Claim 9 (depends on 1) The EOS monitor/protection device of claim 1, further comprising an integrated fuse serially connected to the two conductive structures. ### Claim 10 (depends on 1) The EOS monitor/protection device of claim 1, wherein one of the two conductive structures comprises a partial conductive via contacting a first metal layer at a first end while being separated from the other of the two conductive structures comprising a second metal layer at a second end. ### Claim 11 (depends on 1) The EOS monitor/protection device of claim 1, wherein the two conductive structures is configured to electrically arc in response to the EOS event at a trigger voltage less than about 100V. ### Claim 12 (depends on 1) The EOS monitor/protection device of claim 1, wherein the arcing surfaces of the two conductive structures have different shapes prior to arcing in response to the EOS event. ### Claim 13 (depends on 1) The EOS monitor/protection device of claim 1, wherein the arcing surfaces of the two conductive structures have different shapes when the gap is viewed in one or both of a top down view in a direction perpendicular to a major substrate surface and a side view in a direction parallel to the major substrate surface. ### Claim 14 An electrical overstress (EOS) monitor/protection device comprising a pair of conductive structures that are separated by a deposited dielectric layer serving as an arcing medium and are configured to electrically arc in response to an EOS event, wherein the pair of conductive structures are lithographically defined using a semiconductor fabrication technology and integrated on a semiconductor substrate. ### Claim 15 (depends on 14) The EOS monitor/protection device of claim 14, wherein arcing surfaces of the pair of conductive structures that face each other have different shapes. ### Claim 16 (depends on 14) The EOS monitor/protection device of claim 14, further comprising a sensing circuit configured to detect a change in a physical property of EOS monitor/protection device caused by the EOS event. ### Claim 17 An electrical overstress (EOS) monitor/protection device comprising a pair of conductive structures configured to electrically arc in response to an EOS event, wherein the pair of conductive structures are integrated on a semiconductor substrate and separated by a dielectric layer serving as an arcing medium, wherein one of the pair of conductive structures comprises a doped region in the semiconductor substrate that is doped heavier relative to an adjacent region in the semiconductor substrate, and wherein the other of the pair of conductive structures comprises a conducting via structure laterally overlapping the doped region. ### Claim 18 (depends on 17) The EOS monitor/protection device of claim 17, wherein the conducting via structure comprises a work function tuning metal lining a via formed through a second dielectric layer formed over the dielectric layer and a filler metal filling a remaining volume of the via. ### Claim 19 (depends on 17) The EOS monitor/protection device of claim 17, wherein the doped region and the conducting via structure are interposed by a stack of different dielectric layers serving as the arcing medium. ### Claim 20 (depends on 17) The EOS monitor/protection device of claim 17, wherein one of the pair of conductive structures comprises a metal layer formed over the semiconductor substrate, and wherein the other of the pair of conductive structures comprises a conducting via structure laterally overlapping the doped region.