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US 11,109,750 B2Granted
Pixel array area optimization using stacking scheme for hybrid image sensor with minimal vertical interconnects
AssigneeDePuy Synthes Products, Inc.
InventorLaurent Blanquart
Life of this patent
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Abstract
Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed.
Claims30
An imaging sensor comprising:
- a plurality of substrates including at least a first substrate and a second substrate;
- wherein the first substrate comprises a pixel array comprising a plurality of pixel columns;
- wherein the second substrate comprises a plurality of supporting circuits arranged in a plurality of circuit columns, wherein the plurality of supporting circuits comprise signal processing circuits that receive data from pixels of the pixel array, wherein at least one circuit column at least partially overlaps at least two pixel columns;
- a plurality of pixel column buses and a plurality of circuit column buses;
- a plurality of interconnects, wherein at least one interconnect provides for electrical communication between one circuit column bus and at least one pixel column bus;
- wherein at least a portion of each of the plurality of pixel column buses is superimposed with at least a portion of each of the corresponding plurality of circuit column buses;
- wherein said at least one interconnect is located anywhere along the superimposition of one pixel column bus and one corresponding circuit column bus;
- wherein the second substrate is disposed remotely relative to said first substrate.
5 more elements
An imaging sensor comprising:
- a plurality of substrates comprising at least a first substrate and a second substrate;
- a pixel array disposed on the first substrate and comprising a plurality of pixel columns;
- a plurality of supporting circuits disposed on the second substrate and arranged in a plurality of circuit columns, wherein the plurality of supporting circuits comprise signal processing circuits that receive data from pixels of the pixel array, where at least one circuit column at least partially overlaps with two or more pixel columns;
- a plurality of buses, wherein there is at least one pixel column bus per pixel column residing on the first substrate and at least one circuit column bus per circuit column residing on said second substrate;
- wherein at least a portion of each of the pixel column buses is superimposed with at least a portion of each of the corresponding circuit column buses;
- at least one interconnect providing electrical communication between one pixel column bus and one corresponding circuit column bus;
- and
- wherein said at least one interconnect is located anywhere between one pixel column bus and one corresponding circuit column bus and are superimposed with respect to each other.
5 more elements
An imaging sensor comprising:
- a plurality of substrates including at least a first substrate and a second substrate;
- wherein the first substrate comprises a pixel array comprising a plurality of pixel columns;
- wherein the second substrate comprises a plurality of supporting circuits comprising a plurality of circuit columns, wherein at least one circuit column at least partially overlaps at least two pixel columns;
- a plurality of pixel column buses and a plurality of circuit column buses;
- a plurality of interconnects, wherein at least one interconnect provides for electrical communication between one circuit column bus and at least one pixel column bus;
- wherein at least a portion of each of the plurality of pixel column buses is superimposed with at least a portion of each of the corresponding plurality of circuit column buses;
- wherein said at least one interconnect is located anywhere along the superimposition of one pixel column bus and one corresponding circuit column bus;
- wherein the second substrate is disposed remotely relative to said first substrate;
- wherein electrical connection between one pixel column bus and one circuit column bus is accomplished by two interconnects.
6 more elements
Dependencies are inferred from the claim text.