Method for manufacturing printed wiring board and printed wiring board

A method for manufacturing a printed wiring board, comprising:

• forming a base insulating layer;
• forming a conductor layer on the base insulating layer;
• forming a solder resist layer on the base insulating layer such that the solder resist layer covers the conductor layer;
• forming a first opening in the solder resist layer such that the first opening exposes a first conductor pad of the conductor layer;
• forming a second opening in the solder resist layer such that the second opening exposes a second conductor pad and has a diameter smaller than a diameter of the first opening;
• forming a first bump on the first conductor pad;
• and
• forming a second bump on the second conductor pad such that the second bump has a diameter smaller than a diameter of the first bump,
• wherein the forming of the first bump includes forming a first base plating layer in the first opening, forming a first top plating layer on the first base plating layer, and reflowing the first top plating layer, the forming of the second bump includes forming a second base plating layer in the second opening, forming a second top plating layer on the second base plating layer such that the second top plating layer has an upper surface that is higher than an uppermost position of an upper surface of the first top plating layer prior to reflow of the first and second top plating layers, and reflowing the second top plating layer such that that an uppermost position of the first top plating layer of the first bump is substantially the same as an uppermost position of the second top plating layer of the second bump after the reflow of the first and second top plating layers, and the forming of the first base plating layer and the forming of the second base plating layer comprise forming the first and second base plating layers such that the first and second base plating layers have thicknesses from a surface of the solder resist layer to upper outer peripheral portions of the first and second base plating layers in a same range, that the first base plating layer has a first recess having a depth of 20 μm or less in an upper central portion thereof and that the second base plating layer has a raised portion in an upper central portion thereof, and the forming of the first bump and the forming of the second bump include forming the first bump and the second bump such that a lowermost position of the first top plating layer of the first bump at a middle of the first top plating layer is lower than a lowermost position of the second top plating layer of the second bump at a middle of the second top plating layer.