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US 11,109,016 B2Granted
Methods and apparatus for error detection in an imaging system
AssigneeSemiconductor Components Industries, LLC
InventorsAirell Richard Clark, II, Dwight Poplin
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Abstract
Various embodiments of the present technology may comprise methods and apparatus for error detection in an imaging system. The method and apparatus may comprise pixels arranged in rows and columns and an error detection circuit receiving pixel data generated by the pixels. The error detection circuit may detect errors and generate an error condition and/or signal, for example if one or more image frames are the same and/or a readout error has occurred.
Claims14
A system for detecting errors in image data, comprising:
- a pixel array comprising a plurality of pixels configured to capture an image and generate an image frame comprising a frame of pixel data;
- an image processing unit, coupled to the pixel array and configured to receive the frame of pixel data generated by the pixels, comprising:
- an error detection circuit configured to detect an error condition based on a count value corresponding to individual pixel data transmissions from the frame of pixel data;
- wherein the image processing unit initiates a process to capture and receive new pixel data in response to at the detected error condition;
- and
- an embedded system coupled to the image processing unit to receive output data from the image processing unit,
- wherein the error detection circuit comprises:
- a register configured to store a predetermined value, wherein the predetermined value is greater than the number of pixels in the pixel array;
- an N-bit counter connected to the reaister and configured to receive the predetermined value and generate N bits that represent the count value;
- and
- a logic circuit connected to an output terminal of the N-bit counter and configured to receive each bit of the N-bit count value individually and generate a single output signal according to each bit.
8 more elements
A method for detecting errors in an imaging system, comprising:
- generating a frame of pixel data from a pixel array;
- transmitting the frame of pixel data to an error detection circuit;
- performing error analysis on the frame of pixel data with the error detection circuit using count values corresponding to individual pixel data transmission per frame;
- generating an error signal with the error detection circuit to indicate an error condition;
- operating an image signal processor according to the error signal, where the image signal processor indicates a process to capture and receive new pixel data in response to the error signal;
- and
- preventing use of the second pixel data in response to the error signal,
- wherein performing error analysis with the error detection circuit comprises:
- receiving a predetermined value. wherein the predetermined value is greater than the number of pixels in the pixel array;
- receiving a clock signal that corresponds to a single pixel data transmission;
- counting down from the predetermined value according to the clock signal;
- and
- generating N bits that represent the count value.
10 more elements
An apparatus for error detection, comprising:
- an imaging system comprising:
- a pixel array comprising a plurality of pixels configured to capture an image and generate an image frame comprising a frame of pixel data;
- an error detection circuit coupled to the pixel array and configured to:
- receive the frame of pixel data;
- measure a readout time for the frame of pixel data based on a count value corresponding to individual pixel data transmissions per frame;
- and
- generate an error signal based on the measured readout time;
- and
- an embedded system coupled to the imaging system and responsive to the error signal;
- wherein the error signal prevents the embedded system from using the frame of pixel data,
- wherein the error detection circuit comprises:
- a register configured to store a predetermined value,
- wherein the predetermined value is greater than the number of pixels in the pixel array;
- and
- an N-bit counter connected to the register and configured to receive the predetermined value and generate N bits that represent the count value.
12 more elements
Dependencies are inferred from the claim text.