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US 11,108,704 B2Granted
Use of stashing buffers to improve the efficiency of crossbar switches
AssigneeNVIDIA Corporation
InventorsMatthias Augustin Blumrich, Nan Jiang, Larry Robert Dennison
Life of this patent
Estimating the term…
Abstract
A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.
Claims9
A crossbar switch comprising:
- a plurality of input ports;
- a plurality of output ports;
- a switching fabric interposed between the input ports to the output ports;
- and
- a plurality of stash partitions in a packet recirculating data path through the switching fabric, the recirculating data path bypassing the input ports and the output ports, the stash partitions allocated from port buffer memory.
2 more elements
A switch comprising:
- a first switch fabric coupling a plurality of packet sources to a plurality of packet destinations;
- and
- a second switch fabric also coupling the plurality of packet sources to the plurality of packet destinations;
- and
- a plurality of stash partitions coupled to the first switch fabric and to the second switch fabric, the stash partitions forming a stash storage pool from both of input buffers and output buffers of the switch;
- and
- wherein packets that pass from the packet sources to the packet destinations through the second switch fabric are stored in the stash partitions and are recirculated internally in the switch from the stash partitions to the packet destinations through the first switch fabric.
4 more elements
A crossbar switch comprising:
- a plurality of input ports;
- a plurality of output ports;
- a switch fabric coupled to the plurality of input ports and to the plurality of output ports;
- a buffer memory coupled to one of the plurality of input ports and the plurality of output ports and including:
- a first memory portion allocated as a buffer partition, and
- a second memory portion allocated as a stash partition for recirculating packets through the switching fabric while bypassing the input ports and output ports;
- and
- logic coupled to the buffer memory for controlling allocation of the buffer partition and the stash partition.
5 more elements
Dependencies are inferred from the claim text.