Radiofrequency carrier tracking for amplitude-modulated signals with an unstable reference clock

A phase-locked loop (PLL) circuit comprising:

• a PLL input node to receive a reference clock signal;
• a PLL output node to output a generated clock signal;
• and
• a phase detector, coupled with the PLL input node and the PLL output node to generate a phase tracking signal indicating a phase difference between the reference clock signal and the generated clock signal, the phase tracking signal comprising a first phase tracking signal responsive to a phase of the reference clock signal preceding a phase of the generated clock signal, and a second phase tracking signal responsive to the phase of the generated clock signal preceding the phase of the reference clock signal, the phase detector having a time limiter circuit comprising:
• an absolute phase detection sub-circuit to detect whether the phase tracking signal is asserted by the phase detector;
• a delay timer sub-circuit, coupled with the absolute phase detection sub-circuit to determine, automatically responsive to the absolute phase detection sub-circuit detecting that the phase tracking signal is asserted, whether a signal duration of the phase tracking signal exceeds a threshold duration;
• and
• a pulse gating sub-circuit, coupled with the delay timer sub-circuit to force de-assertion of the phase tracking signal for at least a remainder of a present operating cycle of the PLL automatically responsive to the delay timer sub-circuit determining that the signal duration exceeds the threshold duration.

A method comprising:

• detecting whether a phase tracking signal is asserted by a phase detector of the phase-locked loop (PLL), the phase tracking signal indicating a detected phase difference between an output signal of the PLL and an input reference signal of the PLL;
• determining, automatically responsive to detecting that the phase tracking signal is asserted, whether a signal duration of the phase tracking signal exceeds a threshold duration;
• and
• forcing de-assertion of the phase tracking signal for at least a remainder of a present operating cycle of the PLL automatically responsive to determining that the signal duration exceeds the threshold duration.