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US 11,108,536 B1Granted
Method and apparatus for performing clock and data recovery (CDR)
AssigneeMellanox Technologies, Ltd.
InventorsHananel Faig, David (Dima) Rohlin, Matan Groen
Life of this patent
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Abstract
A method for implementing an efficient clock recovery for multilane high-speed Serializer/Deserializer (SerDes) system having M interleaved lanes, has a non-recursive architecture.
Claims16
A method for efficient multilane Serializer/Deserializer (SerDes) systems, the method comprising:
- receiving a data stream, wherein the data stream comprises a plurality of interleaved lanes, wherein each of the plurality of interleaved lanes comprises a plurality of samples;
- determining, via a non-recursive architecture, an error signal for each of the plurality of interleaved lanes, wherein the error signal for each of the plurality of interleaved lanes is available during a full interleaving cycle;
- generating a correction signal based upon the error signal for each of the plurality of interleaved lanes;
- and
- sampling the data stream based upon the correction signal.
2 more elements
An efficient multilane Serializer/Deserializer (SerDes) system comprising:
- circuitry configured to receive a data stream, wherein the data stream comprises a plurality of interleaved lanes, wherein each of the plurality of interleaved lanes comprises a plurality of samples;
- a non-recursive architecture configured to determine an error signal for each of the plurality of interleaved lanes, wherein the error signal for each of the plurality of interleaved lanes is available during a full interleaving cycle;
- circuitry configured to generate a correction signal based upon the error signals for each of the plurality of interleaved lanes;
- and
- circuitry configured to sample the data stream based upon the correction signal.
2 more elements
Dependencies are inferred from the claim text.