Performance of a bit flipping (BF) decoder of an error correction system
AssigneeSK hynix Inc.
InventorsXuanxuan Lu, Fan Zhang, Aman Bhatia, Meysam Asadi, Haobo Wang
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AssigneeSK hynix Inc.
InventorsXuanxuan Lu, Fan Zhang, Aman Bhatia, Meysam Asadi, Haobo Wang
Estimating the term…
Techniques are described for improving the decoding latency and throughput of an error correction system that includes a bit flipping (BF) decoder, where the BF decoder uses a bit flipping procedure. In an example, different decoding parameters are determined including any of a decoding number of a decoding iteration, a checksum of a codeword, a degree of a variable node, and a bit flipping threshold defined for the bit flipping procedure. Based on one or more of these decoding parameters, a decision can be generated to skip the bit flipping decoding procedure, thereby decreasing the decoding latency and increasing the decoding throughput. Otherwise, the bit flipping decoding procedure can be performed to compute a bit flipping energy and determine whether particular bits are to be flipped or not. Hence, the overall performance (e.g., bit error rate) is not significantly impacted.
A method for decoding a low density parity check (LDPC) codeword, the method implemented by an error correction system that comprises a bit flipping (BF) decoder using a bit flipping procedure, the method comprising:
An error correction system for decoding a low density parity check (LDPC) codeword, the error correction system comprising:
A memory device comprising an error correction system and storing computer-readable instructions, that upon execution by the error correction system that comprises a bit flipping (BF) decoder using a bit flipping procedure for decoding a low density parity check (LDPC) codeword, cause the error correction system to perform operations comprising:
Dependencies are inferred from the claim text.