Low noise integrated circuit techniques
AssigneeAnalog Devices, Inc.
InventorHongxing Li
Life of this patent
Estimating the term…
Abstract
The techniques of this disclosure can cancel or reduce the kT/C noise directly before the gain stage. The effect of the kT/C noise can be greatly reduced, allowing both lower noise conversion and smaller sampling capacitors, which can reduce the die area and reduce the power consumption of the ADC.
Claims25
An integrated circuit configured to reduce or cancel a sampled noise during a sampling phase, the integrated circuit comprising:
- a sampling capacitor configured to store a voltage during the sampling phase, wherein the noise is also stored on the sampling capacitor;
- an amplifier circuit having an input and an output, wherein the input is configured to be coupled to the sampling capacitor;
- a noise cancellation capacitor configured to be coupled to the output of the amplifier circuit, wherein the amplifier circuit is configured to transfer the sampled noise stored on the sampling capacitor to the noise cancellation capacitor;
- and
- a control circuit configured to control switch operation to couple the noise cancellation capacitor to the sampling capacitor to reduce or cancel the sampled noise,
- wherein the control circuit is configured to control switch operation using three phases, and wherein the three phases include:
- a first phase representing the sampling phase of the sampling capacitor;
- a second phase representing a transfer phase in which the sampled noise stored on the sampling capacitor is amplified and sampled by the noise cancellation capacitor;
- and
- a third phase representing a cancellation phase in which the noise cancellation capacitor is coupled to the sampling capacitor to reduce or cancel the sampled noise.
A method to reduce or cancel a sampled noise during a sampling phase, the method comprising:
- storing, during a first phase, a voltage during the sampling phase, wherein the sampled noise is also stored on a sampling capacitor;
- transferring, during a second phase, the sampled noise stored on the sampling capacitor to a noise cancellation capacitor;
- and
- coupling, during a third phase, the noise cancellation capacitor to the sampling capacitor to reduce or cancel the sampled noise.
An integrated circuit configured to reduce or cancel a sampled noise during a sampling phase, the integrated circuit comprising:
- means for storing, during a first phase, a voltage during the sampling phase, wherein the sampled noise is also stored on a sampling capacitor;
- means for transferring, during a second phase, the sampled noise stored on the sampling capacitor to a noise cancellation capacitor;
- and
- means for coupling, during a third phase, the noise cancellation capacitor to the sampling capacitor to reduce or cancel the sampled noise.
An integrated circuit configured to reduce or cancel a sampled noise during a sampling phase, the integrated circuit comprising:
- a first sampling capacitor configured to store a voltage during the sampling phase, wherein the noise is also stored on the first sampling capacitor;
- a second sampling capacitor;
- an amplifier circuit having an input and an output, wherein the input is configured to be coupled to the first sampling capacitor, and wherein the amplifier circuit is configured to transfer the sampled noise stored on the first sampling capacitor;
- a first noise cancellation capacitor configured to be coupled to the output of the amplifier circuit;
- a second noise cancellation capacitor;
- and
- a control circuit configured to control switch operation of a plurality of switches to couple the first noise cancellation capacitor to the second sampling capacitor and the second noise cancellation capacitor to the first sampling capacitor to cancel or reduce the sampled noise.
Dependencies are inferred from the claim text.