Low noise quadrature signal generation

A programmable logic device, comprising:

• a transmit data processing block configured to transmit data using a transmit quadrature clock signal;
• a receive data processing block configured to receive data using a receive quadrature clock signal;
• and
• a quadrature clock generator, coupled to the transmit data processing block and to the receive data processing block, comprising:
• a first injection-locked oscillator configured to generate a plurality of first clock signals based at least in part on a first reference clock signal;
• a first select circuit configured to select one of the first clock signals as the transmit quadrature clock signal;
• a phase interpolator coupled to the first injection-locked oscillator and configured to generate a second reference clock signal based on a selected pair of the first clock signals;
• a second injection-locked oscillator configured to generate a plurality of second clock signals based at least in part on the second reference clock signal;
• and
• a second select circuit configured to select one of the second clock signals as the receive quadrature clock signal.

A method for operating a quadrature clock generator, comprising:

• generating a plurality of first clock signals based at least in part on a first reference clock signal;
• selecting one of the plurality of first clock signals as a transmit quadrature clock signal;
• generating a second reference clock signal by interpolating between a pair of the plurality of first clock signals;
• generating a plurality of second clock signals based at least in part on the second reference clock signal;
• and
• selecting one of the plurality of second clock signals as a receive quadrature clock signal.