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US 11,108,400 B1Granted
Hitless switching by resetting multi-modulus feedback divider
AssigneeRenesas Electronics America Inc.
InventorGreg Armstrong
Life of this patent
Estimating the term…
Abstract
An apparatus includes a plurality of monitoring circuits and a reset circuit. The monitoring circuits may each be configured to determine a status of one of a plurality of input signals, transmit one of the input signals to a PLL circuit and generate a loss signal in response to the status. The reset circuit may be configured to receive the loss signal and generate a reset signal in response to the loss signal. One of the input signals may be a primary input used by the PLL circuit. One of the input signals may be a secondary input that has been selected to replace the primary input. The reset signal may be configured to reset a feedback clock divider of the PLL circuit.
Claims19
An apparatus comprising:
- a plurality of monitoring circuits each configured to (i) determine a status of one of a plurality of input clock signals, (ii) transmit one of said plurality of input clock signals to a phase-locked loop circuit, and (iii) generate a loss signal in response to said status;
- and
- a reset circuit configured to (i) receive said loss signal from said plurality of monitoring circuits and (ii) generate a reset signal in response to said loss signal, wherein (a) one of said plurality of input clock signals is a primary input used by said phase-locked loop circuit, (b) one of said plurality of input clock signals is a secondary input that has been selected to replace said primary input for said phase-locked loop circuit, (c) said reset signal is configured to reset a feedback clock divider of said phase-locked loop circuit, (d) a feedback reset circuit is implemented as a component of said feedback clock divider, (e) said feedback reset circuit is configured to reset a feedback signal generated by said feedback clock divider based on an output clock signal of said phase-locked loop circuit and (f) resetting said feedback clock divider limits an inaccuracy in measuring an offset between said primary input and said secondary input in a hitless re-arrangement of said input clock signals.
An apparatus comprising:
- a plurality of monitoring circuits each configured to (i) determine a status of one of a plurality of input clock signals, (ii) transmit one of said plurality of input clock signals to a phase-locked loop circuit, and (iii) generate a loss signal in response to said status;
- and
- a reset circuit configured to (i) receive said loss signal from said plurality of monitoring circuits and (ii) generate a reset signal in response to said loss signal, wherein (a) one of said plurality of input clock signals is a primary input used by said phase-locked loop circuit, (b) one of said plurality of input clock signals is a secondary input that has been selected to replace said primary input for said phase-locked loop circuit, (c) said reset signal is configured to reset a feedback clock divider of said phase-locked loop circuit, (d) resetting said feedback clock divider limits an inaccuracy in measuring an offset between said primary input and said secondary input in a hitless re-arrangement of said input clock signals and (e) said apparatus is configured to limit a phase transient on an output clock of said phase-locked loop circuit.
An apparatus comprising:
- a plurality of monitoring circuits each configured to (i) determine a status of one of a plurality of input clock signals, (ii) transmit one of said plurality of input clock signals to a phase-locked loop circuit, and (iii) generate a loss signal in response to said status;
- and
- a reset circuit configured to (i) receive said loss signal from said plurality of monitoring circuits and (ii) generate a reset signal in response to said loss signal, wherein (a) one of said plurality of input clock signals is a primary input used by said phase-locked loop circuit, (b) one of said plurality of input clock signals is a secondary input that has been selected to replace said primary input for said phase-locked loop circuit, (c) said reset signal is configured to reset a feedback clock divider of said phase-locked loop circuit and (d) resetting said feedback clock divider is configured to limit (i) an inaccuracy in measuring an offset between said primary input and said secondary input in a hitless re-arrangement of said input clock signals and (ii) an amount of time for said phase-locked loop circuit to perform a phase offset measurement.
Dependencies are inferred from the claim text.