US 11,108,396 B2 · Multivoltage high voltage IO in low voltage technology

Abstract

A multi-voltage, high voltage I/O buffer in low-voltage technology is disclosed. In one embodiment, the I/O buffer includes a logic circuit configured to generate a signal based on a data signal and a first control signal. A level shifter is coupled between a supply voltage terminal and a ground terminal, and the level shifter is generates first and second output signals in first and second voltage domains, respectively, at first and second nodes, respectively, based on the signal from the logic circuit. A control circuit is coupled between the second node and a third node. The control circuit transmits the second output signal to the third node when the first control signal is asserted, and the control circuit couples the third node to the ground terminal when the first control signal is not asserted.

Claims20

Dependent claims

An integrated circuit (IC) comprising:

an input/output (I/O) buffer comprising:
a logic circuit configured to generate a signal based on a data signal and a first control signal;
a level shifter coupled between a supply voltage terminal and a ground terminal, wherein the level shifter is configured to generate first and second output signals in first and second voltage domains, respectively, at first and second nodes, respectively, based on the signal from the logic circuit;
a control circuit coupled between the second node and a third node, wherein the control circuit transmits the second output signal to the third node when the first control signal is asserted, and wherein the control circuit couples the third node to the ground terminal when the first control signal is not asserted.

1 more element

An integrated circuit (IC) comprising:

an input/output (I/O) buffer comprising:
an I/O pad;
a logic circuit configured to generate a signal based on first and second input signals;
a level shifter configured to generate first and second output signals based on the signal from the logic circuit;
a control circuit configured to receive the second output signal and the first input signal;
an output stage configured to drive the I/O pad, wherein the output stage comprises first and second transistors;
wherein the control circuit is configured to activate or deactivate the second transistor based on the second output signal while the first input signal is asserted;
wherein the control circuit is configured to deactivate the second transistor while the first input signal is not asserted.

5 more elements

An integrated circuit (IC) comprising:

an input/output (I/O) buffer comprising:
an I/O pad;
an output stage configured to drive the I/O pad;
a logic circuit configured to generate a binary output signal based on first and second binary input signals;
a level shifter configured to generate first and second binary output signals based on the binary output signal from the logic circuit;
a control circuit configured to receive the first binary input signal and the second binary output signal;
wherein the control circuit is configured to control the output stage based on the first binary input signal and the second binary output signal.

4 more elements

Dependencies are inferred from the claim text.

Multivoltage high voltage IO in low voltage technology

Life of this patent

Multivoltage high voltage IO in low voltage technology

Life of this patent

Abstract

Claims20