Memory cell and memory cell array of magnetoresistive random access memory operated by negative voltage
AssigneeeMemory Technology Inc.
InventorChia-Fu Chang
Life of this patent
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Abstract
A memory cell of MRAM includes a PMOS transistor and a storage element. A first terminal of the PMOS transistor is connected with a first end of the memory cell. A control terminal of the PMOS transistor is connected with a second end of the memory cell. A first terminal of the storage element is connected with a second terminal of the PMOS transistor. A second terminal of the storage element is connected with a third end of the memory cell. During a write operation, a first voltage is provided to the first end of the memory cell, a second voltage is provided to the third end of the memory cell, and a control voltage is provided to the second end of the memory cell. Consequently, the memory cell is in a first storage state.
Claims14
A memory cell of a magnetoresistive random access memory, the memory cell comprising:
- a PMOS transistor, wherein a first terminal of the PMOS transistor is connected with a first end of the memory cell, and a control terminal of the PMOS transistor is connected with a second end of the memory cell;
- and
- a storage element, wherein a first terminal of the storage element is connected with a second terminal of the PMOS transistor, and a second terminal of the storage element is connected with a third end of the memory cell,
- wherein while a write operation is performed, a first voltage is provided to the first end of the memory cell, a second voltage is provided to the third end of the memory cell, and a control voltage is provided to the second end of the memory cell, so that the memory cell is in a first storage state,
- wherein a magnitude of the first voltage is higher than a magnitude of the second voltage, and the magnitude of the second voltage is higher than a magnitude of the control voltage.
A memory cell array of a magnetoresistive random access memory, the memory cell array comprising:
- a first memory cell comprising a first PMOS transistor and a first storage element;
- and
- a second memory cell comprising a second PMOS transistor and a second storage element;
- wherein a first terminal of the first PMOS transistor is connected with a first end of the first memory cell, a control terminal of the first PMOS transistor is connected with a word line, a first terminal of the first storage element is connected with a second terminal of the first PMOS transistor, and a second terminal of the first storage element is connected with a second end of the first memory cell,
- wherein a first terminal of the second PMOS transistor is connected with a first end of the second memory cell, a control terminal of the second PMOS transistor is connected with the word line, a first terminal of the second storage element is connected with a second terminal of the second PMOS transistor, and a second terminal of the second storage element is connected with a second end of the second memory cell,
- wherein while a write operation is performed, a control voltage is provided to the word line, a first voltage difference is provided to two terminals of the first storage element, a second voltage difference is provided to two terminals of the second storage element, so that the first memory cell is in a first storage state and the second memory cell is in a second storage state,
- wherein while the write operation is performed, a first voltage is provided to the first end of the first memory cell, a second voltage is provided to the second end of the first memory cell, the second voltage is provided to the first end of the second memory cell, the first voltage is provided to the second end of the second memory cell, a magnitude of the first voltage is higher than a magnitude of the second voltage, and the magnitude of the second voltage is higher than a magnitude of the control voltage.
Dependencies are inferred from the claim text.