Clock phase control

A clock phase control circuit, comprising:

• a shift register divider module including a plurality of shift registers configured as a frequency divider to produce one or more phase clock signals based on an oscillating input clock signal, each of the one or more phase clock signals having a different frequency than the input clock signal;
• and
• a multiplexer configured to produce an output clock signal by selecting one of the one or more phase clock signals
• wherein the shift register divider module comprises at least one shift register in series with first and second exclusive-or (XOR) gates, the first and second XOR gates arranged in parallel with each other, wherein an input of the first XOR gate is connected to a logically low signal, wherein an output of the first XOR gate is connected to a first input of the multiplexer, wherein an input of the second XOR gate is connected to a logically high signal, and wherein an output of the second XOR gate is connected to a second input of the multiplexer.

A method of producing a phase clock signal, the method comprising:

• producing, using a clock input gate module and based on an oscillating input clock signal, a first intermediate clock signal and a second intermediate clock signal;
• producing, using a first shift register divider module, at least one first phase clock signal based on the first intermediate clock signal, the at least one first phase clock signal having a different frequency than the first intermediate clock signal;
• producing, using a second shift register divider module, at least one second phase clock signal based on the second intermediate clock signal, the at least one second phase clock signal having a different frequency than the second intermediate clock signal;
• and
• producing, using a multiplexer, an output clock signal by selecting one of the at least one first phase clock signal and the at least one second phase clock signal.