RRAM structure

An integrated chip, comprising:

• a bottom electrode arranged over an etch stop material over a substrate;
• a data storage structure disposed over the bottom electrode and configured to store a data state;
• a top electrode disposed on an upper surface of the data storage structure;
• a first interconnect via contacting an upper surface of the bottom electrode;
• a second interconnect via contacting an upper surface of the top electrode;
• an interconnect wire contacting a top of the first interconnect via;
• a third interconnect via contacting a bottom of the interconnect wire and extending through the etch stop material to a plurality of lower interconnect layers coupled to an access device;
• and
• a sidewall spacer disposed over the bottom electrode and along opposing sidewalls of the data storage structure and the top electrode, wherein the bottom electrode extends past opposing outermost sides of the sidewall spacer.

A method of forming an integrated chip, comprising:

• forming an etch stop material over a lower inter-level dielectric (ILD) structure on a substrate;
• sequentially depositing a bottom electrode layer, a data storage layer, and a top electrode layer, over the etch stop material;
• performing a first patterning process on the top electrode layer and the data storage layer according to a first masking layer to define a top electrode and a data storage structure;
• forming a sidewall spacer along opposing sides of the top electrode and the data storage structure;
• performing a second patterning process on the bottom electrode layer according to a second masking layer to define a bottom electrode that laterally extends past outermost edges of the sidewall spacer along a first pair of opposing directions and along a second pair of opposing directions that are perpendicular to the first pair of opposing directions, the first pair of opposing directions and the second pair of opposing directions parallel to an upper surface of the etch stop material;
• forming an upper ILD structure over the etch stop material;
• and
• forming a first interconnect via and a second interconnect via within the upper ILD structure, wherein the first interconnect via contacts an upper surface of the bottom electrode and the second interconnect via contacts an upper surface of the top electrode.