US 11,107,979 B2Granted

Patterned silicide structures and methods of manufacture

AssigneeSpin Memory, Inc.

InventorsKuk-Hwan Kim, Dafna Beery, Marcin Gajek, Michail Tzoufras, Kadriye Deniz Bozdag, Eric Ryan, Satoru Araki, Andy Walker

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Abstract

Aspects of the present technology are directed toward Integrated Circuits (IC) including a plurality of trenches disposed in a substrate about a set of silicide regions. The trenches can extend down into the substrate below the set of silicide regions. The silicide regions can be formed by implanting metal ions into portions of a substrate exposed by a mask layer with narrow pitch openings. The trenches can be formed by selectively etching the substrate utilizing the set of silicide regions as a trench mask. An semiconductor material with various degree of crystallinity can be grown from the silicide regions, in openings that extend through subsequently formed layers down to the silicide regions.

Claims20

Dependent claims

A method of forming an interconnect in an Integrated Circuit (IC) comprising:

forming a first set of silicide regions in portions of a substrate;
selectively etching the substrate to form a plurality of trenches into the substrate along-side the first set of silicide regions and extending below the first set of silicide regions;
filling the trenches with a first dielectric layer:
forming a second dielectric layer, a conductive layer and a third dielectric layer over the first set of silicide regions and the first dielectric layer filling the trenches;
selectively etching the second dielectric layer, the conductive layer and the third dielectric layer to form a plurality of openings substantially aligned to the first set of silicide regions, wherein sets of the plurality of openings extend to corresponding ones of the first set of silicide regions;
forming a fourth dielectric layer on exposed surfaces of the one or more conductive layers in the plurality of openings;
and
forming an semiconductor material with various degree of crystallinity in the plurality of openings after formation of the fourth dielectric layer.

5 more elements

A method of forming a Magnetic Tunnel Junction (MTJ) memory array comprising:

forming a mask on a semiconductor substrate, wherein the mask includes openings with a large length to width ratio;
forming a first set of silicide regions in portions of the semiconductor substrate exposed by the openings in the mask;
selectively etching the semiconductor substrate to form a set of trenches into the semiconductor substrate self-aligned to the first set of silicide regions and extending below the first set of silicide regions;
depositing a nitride layer on the walls of the trenches;
depositing a first dielectric layer in the trenches after formation of the nitride layer:
depositing a second dielectric layer over the first set of silicide regions and the first dielectric layer in the trenches;
depositing a first conductive layer over the second dielectric layer;
depositing a third dielectric layer over the first conductive layer;
selectively etching through the third dielectric layer, the first conductive layer and the second dielectric layer to form a plurality of holes substantially aligned to the first set of silicide regions;
depositing a fourth dielectric layer on the walls of the plurality of holes;
and
epitaxially depositing a semiconductor in the plurality of holes after formation of the fourth dielectric layer on the walls of the plurality of holes.

9 more elements

A method of forming a Magnetic Tunnel Junction (MTJ) memory array comprising:

forming a first silicide region in a semiconductor substrate;
forming a mask on a semiconductor substrate, wherein the mask includes openings with a large length to width ratio;
selectively etching the semiconductor substrate exposed by the mask to form a set of trenches into the semiconductor substrate and a first set of silicide regions disposed between the trenches, wherein the trenches extend below the first set of silicide regions;
depositing a nitride layer on the walls of the trenches;
depositing a first dielectric layer in the trenches after formation of the nitride layer:
depositing a second dielectric layer over the first set of silicide regions and the first dielectric layer in the trenches;
depositing a first conductive layer over the second dielectric layer;
depositing a third dielectric layer over the first conductive layer;
selectively etching through the third dielectric layer, the first conductive layer and the second dielectric layer to form a plurality of holes substantially aligned to the first set of silicide regions;
depositing a fourth dielectric layer on the walls of the plurality of holes;
and
epitaxially depositing a semiconductor in the plurality of holes after formation of the fourth dielectric layer on the walls of the plurality of holes.

9 more elements

Dependencies are inferred from the claim text.