Majorana fermion quantum computing devices fabricated with ion implant methods

A computer-implemented method to fabricate a quantum computing device, the method comprising:

• forming, on a superconductor layer, a first resist pattern defining a device region and a sensing region within the device region;
• removing, using an etching process, the superconductor layer within the sensing region, the etching exposing a region of an underlying semiconductor layer outside the device region unprotected by the first resist pattern;
• implanting the exposed region of the semiconductor layer, the implanting forming an isolation region surrounding the device region;
• exposing, using an etching process subsequent to the implanting, the sensing region and a portion of the device region of the superconductor layer adjacent to the isolation region;
• forming, by depositing a first metal layer within the sensing region, a tunnel junction gate;
• forming a sensing region gate by coupling the semiconductor layer with a second metal layer;
• and
• forming a nanorod contact using the second metal within the portion of the device region outside the sensing region.

A superconductor fabrication system comprising a lithography component, the superconductor fabrication system configured to fabricate a quantum computing device performing operations comprising:

• forming, on a superconductor layer, a first resist pattern defining a device region and a sensing region within the device region;
• removing, using an etching process, the superconductor layer within the sensing region, the etching exposing a region of an underlying semiconductor layer outside the device region unprotected by the first resist pattern;
• implanting the exposed region of the semiconductor layer, the implanting forming an isolation region surrounding the device region;
• exposing, using an etching process subsequent to the implanting, the sensing region and a portion of the device region of the superconductor layer adjacent to the isolation region;
• forming, by depositing a first metal layer within the sensing region, a tunnel junction gate;
• forming a sensing region gate by coupling the semiconductor layer with a second metal layer;
• and
• forming a nanorod contact using the second metal within the portion of the device region outside the sensing region.