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US 11,107,924 B2Granted
Systems and methods to reduce FinFET gate capacitance
AssigneeIntel Corporation
InventorsAaron D. Lilak, Rishabh Mehandru, Patrick Morrow
Life of this patent
Estimating the term…
Abstract
The disclosure illustrates systems and methods for removing at least some excess gate material of a FinFET transistor. A FinFET transistor with the excess gate material removed may include a gate with a T-shaped cross-section. The narrower portion of the cross-section may be processed using backside wafer processing. The width of the narrower portion may be defined by a spacer.
Claims20
A transistor comprising:
- a source region located on a first side of a substrate;
- a drain region located on the first side of the substrate;
- a semiconductor fin coupling the source region to the drain region, the semiconductor fin having a first portion located near the first side of the substrate and a second portion located near a second side of the substrate, wherein the first and the second sides of the substrate are opposite each other;
- a spacer at least partially surrounding the second portion of the semiconductor fin and extending out from the semiconductor fin a first distance;
- and
- a gate at least partially surrounding the first portion of the semiconductor fin, the gate having a T-shaped cross-section with a wider portion and a narrower portion, the wider portion of the gate being located nearer an end of the first portion of the semiconductor fin than the narrower portion.
3 more elements
A method comprising:
- forming at least one FinFET transistor on a first side of a wafer, the FinFET transistor comprising a source, a drain, a fin, and a gate, the gate at least partially surrounding the fin at a proximal portion and extending out from the fin a first distance;
- removing a first portion of a second side of the wafer to expose a distal portion of the fin of the FinFET transistor, wherein the first and the second sides of the wafer are opposite each other;
- forming a spacer around the distal portion of the fin, the spacer extending out from the fin a second distance, wherein the second distance is less than the first distance;
- and
- removing a second portion of the second side of the wafer and a portion of the gate, wherein the portion of the gate removed is defined by the spacer.
2 more elements
A computing device comprising one or more transistors, each of the one or more transistors comprising:
- a source region located on a first side of a substrate;
- a drain region located on the first side of the substrate;
- a semiconductor region configured as a channel coupling the source region to the drain region, the semiconductor region forming a fin with a distal portion of the fin located near the first side of the substrate and a proximal portion of the fin located near a second side of the substrate, wherein the first and the second sides of the substrate are opposite each other;
- and
- an electrically conductive material at least partially surrounding the distal portion of the fin, the electrically conductive material having a T-shaped cross-section with a wider portion and a narrower portion, the wider portion of the electrically conductive material being located nearer an end of the distal portion of the fin than the narrower portion.
2 more elements
Dependencies are inferred from the claim text.