Gate structure and method with enhanced gate contact and threshold voltage

A method, comprising:

• forming isolation features in a semiconductor substrate, defining first fins in a first region and second fins in a second region;
• forming a first dummy gate stack on the first fins and a second dummy gate stack on the second fins;
• depositing an inter-layer dielectric (ILD) layer on the substrate;
• removing the first and second dummy gate stacks by an etching process, resulting a first gate trench and a second gate trench in the ILD layer;
• depositing a first tantalum titanium nitride layer in the first and second gate trenches;
• depositing a titanium aluminum nitride layer on the first tantalum titanium nitride layer to fill in the first and second gate trench;
• forming a patterned mask to cover the second region and uncover the first region;
• performing an etching process to the titanium aluminum nitride layer in the first gate trench such that the titanium aluminum nitride layer is recessed;
• depositing a second tantalum titanium nitride layer on the recessed titanium aluminum nitride layer in the first gate trench;
• and
• filling a low resistance metal in the first gate trench, thereby forming a first gate stack in the first gate trench and a second gate stack in the second gate trench, and wherein the first and second gate stacks are different in structure.

A method, comprising:

• forming isolation features in a semiconductor substrate, defining first fins in a first region and second fins in a second region;
• forming a first dummy gate stack on the first fins and a second dummy gate stack on the second fins;
• depositing an inter-layer dielectric (ILD) layer on the substrate;
• removing the first and second dummy gate stacks by an etching process, resulting a first gate trench and a second gate trench in the ILD layer;
• depositing a first tantalum titanium nitride layer in the first and second gate trenches;
• depositing a titanium aluminum nitride layer on the first tantalum titanium nitride layer to fill in the first and second gate trench;
• forming a patterned mask to cover the second region and uncover the first region;
• performing an etching process to the titanium aluminum nitride layer in the first gate trench such that the titanium aluminum nitride layer is recessed;
• depositing a second tantalum titanium nitride layer on the recessed titanium aluminum nitride layer in the first gate trench;
• and
• filling a low resistance metal in the first gate trench,
• thereby forming a first gate stack is formed in the first gate trench and a second gate stack in the second gate trench, and wherein the first gate stack is free of the low resistance metal.