Source/drain recess in a semiconductor device

A transistor device, comprising:

• a gate stack disposed on and interfacing a top surface of a substrate having a dielectric spacer element abutting a sidewall of the gate stack, wherein a portion of the top surface of the substrate extends along a bottom of the dielectric spacer element;
• a recess disposed in the substrate, wherein the recess is disposed below the portion of the top surface of the substrate, the recess having:
• a first profile having a first substantially linear sidewall extending under the gate stack and a second substantially linear sidewall opposing the first substantially linear sidewall, wherein a width between the first substantially linear sidewall and the second substantially linear sidewall increases with an increasing distance below the top surface of the substrate;
• and
• a second profile contiguous with and below the first profile, the second profile providing a v-bottom shape defined at least in part by a third substantially linear sidewall and a fourth substantially linear sidewall, wherein a width between the third substantially linear sidewall and the fourth substantially linear sidewall decreases with an increasing distance below the top surface of the substrate;
• and
• wherein the recess is filled with a semiconductor material.

A transistor device, comprising:

• a gate stack disposed on and interfacing a top surface of a silicon substrate having a dielectric spacer element abutting a sidewall of the gate stack, wherein a portion of the top surface of the silicon substrate extends along a bottom of the dielectric spacer element;
• a recess disposed in the silicon substrate, wherein the recess is disposed below the portion of the top surface of the silicon substrate, the recess having:
• a first profile having a first substantially linear sidewall extending under the gate stack and a second substantially linear sidewall opposing the first substantially linear sidewall, wherein a width between the first substantially linear sidewall and the second substantially linear sidewall increases with an increasing distance below the top surface of the silicon substrate;
• and
• a second profile contiguous with and below the first profile, the second profile providing a v-bottom shape defined at least in part by a third substantially linear sidewall and a fourth substantially linear sidewall, wherein a width between the third substantially linear sidewall and the fourth substantially linear sidewall decreases with an increasing distance below the top surface of the silicon substrate;
• a third profile above the first profile and contiguous with the first profile, wherein the third profile includes a fifth substantially linear sidewall and a sixth substantially linear sidewall opposing the fifth substantially linear sidewall, wherein the fifth and sixth substantially linear sidewalls are substantially vertical with respect to the top surface of the silicon substrate;
• and
• wherein the recess is filled with an epitaxially grown semiconductor material.