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US 11,107,920 B2Granted
Methods of forming dislocation enhanced strain in NMOS structures
AssigneeIntel Corporation
InventorsMichael Jackson, Anand Murthy, Glenn Glass, Saurabh Morarka, Chandra Mohapatra
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Abstract
Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.
Claims10
A semiconductor structure, comprising:
- a silicon body extending from a single crystalline silicon substrate through an isolation region, the isolation region having a top surface, and the silicon body having a top and laterally opposite sidewalls, wherein the top of the silicon body is above the top surface of the isolation region;
- a gate electrode over the top of the silicon body and adjacent to the laterally opposite sidewalls of the silicon body, the gate electrode over a portion of the isolation region, and the gate electrode defining a channel region in the silicon body;
- a first silicon germanium dislocation nucleation layer in a first recess in the silicon body laterally adjacent a first end of the channel region at a first side of the gate electrode;
- a silicon source region on the first silicon germanium dislocation nucleation layer, the silicon source region comprising a first plurality of dislocations;
- a second silicon germanium dislocation nucleation layer in a second recess in the silicon body laterally adjacent a second end of the channel region at a second side of the gate electrode, the second side of the gate electrode opposite the first side of the gate electrode;
- a silicon drain region on the second silicon germanium dislocation nucleation layer, the silicon drain region comprising a second plurality of dislocations, wherein a top of the silicon drain region is spaced apart from a top of the silicon source region by a first distance, and a bottom of the silicon drain region is spaced apart from a bottom of the silicon source region by a second distance greater than the first distance;
- a first dielectric spacer adjacent the first side of the gate electrode;
- and
- a second dielectric spacer adjacent the second side of the gate electrode.
6 more elements
A system, comprising:
- a circuit board;
- and
- a package structure coupled to the circuit board, the package structure comprising a die coupled to a package, the die comprising:
- a silicon body extending from a single crystalline silicon substrate through an isolation region, the isolation region having a top surface, and the silicon body having a top and laterally opposite sidewalls, wherein the top of the silicon body is above the top surface of the isolation region;
- a gate electrode over the top of the silicon body and adjacent to the laterally opposite sidewalls of the silicon body, the gate electrode over a portion of the isolation region, and the gate electrode defining a channel region in the silicon body;
- a first silicon germanium dislocation nucleation layer in a first recess in the silicon body laterally adjacent a first end of the channel region at a first side of the gate electrode;
- a silicon source region on the first silicon germanium dislocation nucleation layer, the silicon source region comprising a first plurality of dislocations;
- a second silicon germanium dislocation nucleation layer in a second recess in the silicon body laterally adjacent a second end of the channel region at a second side of the gate electrode, the second side of the gate electrode opposite the first side of the gate electrode;
- a silicon drain region on the second silicon germanium dislocation nucleation layer, the silicon drain region comprising a second plurality of dislocations, wherein a top of the silicon drain region is spaced apart from a top of the silicon source region by a first distance, and a bottom of the silicon drain region is spaced apart from a bottom of the silicon source region by a second distance greater than the first distance;
- a first dielectric spacer adjacent the first side of the gate electrode;
- and
- a second dielectric spacer adjacent the second side of the gate electrode.
9 more elements
Dependencies are inferred from the claim text.