Semiconductor structure for fully depleted silicon-on-insulator (FDSOI) transistor

A semiconductor structure, comprising:

• a semiconductor substrate;
• an N-type well region over the semiconductor substrate;
• an undoped layer over the semiconductor substrate and in contact with the N-type well region;
• a fully depleted silicon-on-insulator (FDSOI) transistor formed over the N-type well region, comprising:
• a buried oxide layer over the N-type well region;
• a source region over the buried oxide layer;
• a drain region over the buried oxide layer;
• a silicon-on-insulator (SOI) layer over the buried oxide layer and between the source and drain regions;
• and
• a metal gate over the SOI layer;
• a first shallow trench isolation (STI) region over the undoped layer;
• a first P-type doped region over the undoped layer, wherein the first P-type doped region is separated from the drain region of the FDSOI transistor by the first STI region;
• and
• a first interconnection element over the first P-type doped region and configured to connect the first P-type doped region to a ground.

A semiconductor structure, comprising:

• a semiconductor substrate;
• an undoped layer over the semiconductor substrate;
• a N-type well region over the semiconductor substrate and between a first region and a second region of the undoped layer;
• a fully depleted silicon-on-insulator (FDSOI) transistor formed over the N-type well region, comprising:
• a buried oxide layer over the N-type well region;
• a source region over the buried oxide layer;
• a drain region over the buried oxide layer;
• a silicon-on-insulator (SOI) layer over the buried oxide layer and between the source and drain regions;
• and
• a metal gate over the SOI layer;
• a first shallow trench isolation (STI) region over the first region of the undoped layer;
• a first P-type doped region over the first region of the undoped layer, wherein the first P-type doped region is separated from the drain region of the FDSOI transistor by the first STI region;
• a second STI region over the second region of the undoped layer;
• and
• a second P-type doped region over the second region of the undoped layer, wherein the second P-type doped region is separated from the source region of the FDSOI transistor by the second STI region.