High voltage transistor structure

A device comprising:

• a first buried layer over a substrate;
• a second buried layer over the first buried layer;
• a first well over the first buried layer and the second buried layer;
• a first high voltage well, a second high voltage well, and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well;
• a first drain/source region in the first high voltage well;
• a first gate electrode over the first well;
• a second drain/source region in the second high voltage well;
• and
• a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.

An apparatus comprising:

• a first buried layer over a substrate;
• a second buried layer over the first buried layer;
• a first well over the first buried layer and the second buried layer;
• a first high voltage well, a second high voltage well, and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the second high voltage well;
• a first drain/source region in the first high voltage well;
• a first gate electrode over the first well;
• a second drain/source region in the second high voltage well;
• a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode;
• a third drain/source region in the third high voltage well;
• a second gate electrode formed over the first well;
• and
• a second isolation region in the second high voltage well, and between the second drain/source region and the second gate electrode.