Metal-oxide semiconductor for field-effect transistor having enhanced high-frequency performance

A laterally-diffused metal-oxide semiconductor (LDMOS) device, comprising:

• a semiconductor substrate of a first conductivity type;
• a doped drift region of a second conductivity type formed on at least a portion of the substrate, proximate an upper surface thereof, the second conductivity type being opposite to the first conductivity type;
• a body region of the first conductivity type formed in the doped drift region proximate an upper surface of the doped drift region;
• source and drain regions of the second conductivity type formed proximate an upper surface of the body region and doped drift region, respectively, and spaced laterally from one another;
• a gate formed over at least a portion of the body region and between the source and drain regions, the gate being electrically isolated from the body region by a first insulating layer disposed between the gate and the body region;
• and
• a shielding structure formed over at least a portion of the doped drift region, the shielding structure being formed on at least a portion of a second insulating layer disposed between the shielding structure and the doped drift region, at least one portion of the gate and shielding structure being spaced laterally from one another to thereby reduce parasitic gate-to-drain capacitance in the LDMOS device;
• wherein the shielding structure includes a plurality of openings therein exposing the doped drift region through said openings, a parasitic gate-to-drain capacitance in the LDMOS device being controlled as a function of dimensions of each of the openings in the shielding structure.

A laterally-diffused metal-oxide semiconductor (LDMOS) device, comprising:

• a semiconductor substrate of a first conductivity type;
• a doped drift region of a second conductivity type formed on at least a portion of the substrate, proximate an upper surface thereof, the second conductivity type being opposite to the first conductivity type;
• a body region of the first conductivity type formed in the doped drift region proximate an upper surface of the doped drift region;
• source and drain regions of the second conductivity type formed proximate an upper surface of the body region and doped drift region, respectively, and spaced laterally from one another;
• a gate formed over at least a portion of the body region and between the source and drain regions, the gate being electrically isolated from the body region by a first insulating layer disposed between the gate and the body region;
• a shielding structure formed over at least a portion of the doped drift region, the shielding structure being formed on at least a portion of a second insulating layer disposed between the shielding structure and the doped drift region, at least one portion of the gate and shielding structure being spaced laterally from one another to thereby reduce parasitic gate-to-drain capacitance in the LDMOS device;
• a gate electrode;
• and
• at least first and second conductive vias, the first conductive via electrically connecting the gate with the gate electrode at an end of the gate, the second conductive via electrically connecting the shielding structure with the gate electrode at an end of the shielding structure adjacent to the first conductive via.

A laterally-diffused metal-oxide semiconductor (LDMOS) device, comprising:

• a semiconductor substrate of a first conductivity type;
• a doped drift region of a second conductivity type formed on at least a portion of the substrate, proximate an upper surface thereof, the second conductivity type being opposite to the first conductivity type;
• a body region of the first conductivity type formed in the doped drift region proximate an upper surface of the doped drift region;
• source and drain regions of the second conductivity type formed proximate an upper surface of the body region and doped drift region, respectively, and spaced laterally from one another;
• a gate formed over at least a portion of the body region and between the source and drain regions, the gate being electrically isolated from the body region by a first insulating layer disposed between the gate and the body region;
• a shielding structure formed over at least a portion of the doped drift region, the shielding structure being formed on at least a portion of a second insulating layer disposed between the shielding structure and the doped drift region, at least one portion of the gate and shielding structure being spaced laterally from one another to thereby reduce parasitic gate-to-drain capacitance in the LDMOS device;
• first and second conductive vias;
• a gate electrode disposed on and electrically connected with the first conductive via;
• and
• a shielding structure electrode disposed on and electrically connected with the second conductive via;
• wherein the gate and shielding structure electrodes are adapted for connection with a gate driver circuit for providing a high-impedance electrical connection between the gate and shielding structure.