US 11,107,911 B2Granted

Semiconductor device and method for manufacturing same

AssigneeDenso Corporation

InventorsYuichi Takeuchi, Shuhei Mitani, Yasuhiro Ebihara, Yusuke Yamashita, Tadashi Misumi

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Abstract

A semiconductor device includes an inversion type semiconductor element, which has: a substrate; a drift layer; a saturation current suppression layer; a current dispersion layer; a base region; a source region; a connection layer; a plurality of trench gate structures; an interlayer insulation film; a source electrode; and a drain electrode. A channel region is provided in a portion of the base region in contact with each trench gate structure by applying a gate voltage to the gate electrode and applying a normal operation voltage as a drain voltage to the drain electrode; and a current flows between the source electrode and the drain electrode through the source region and the JFET portion.

Claims17

Dependent claims

A semiconductor device comprising an inversion type semiconductor element, the semiconductor element including:

a substrate having a first conductivity type or a second conductivity type and made of semiconductor;
a drift layer arranged on the substrate and made of semiconductor having the first conductivity type with an impurity concentration lower than the substrate;
a saturation current suppression layer disposed on the drift layer and including:
a plurality of electric field block layers made of semiconductor having the second conductivity type and arranged in a stripe pattern along one direction a longitudinal direction;
and a JFET portion made of semiconductor having the first conductivity type and including a plurality of portions which are arranged in a stripe pattern and alternately arranged with the electric field block layer;
a current dispersion layer made of semiconductor having the first conductivity type with a first conductivity type impurity concentration higher than the drift layer and arranged on the saturation current suppression layer;
a base region made of semiconductor having the second conductivity type and disposed on the current dispersion layer;
a source region made of semiconductor having the first conductivity type with the first conductivity type impurity concentration higher than the drift layer and disposed on the base region;
a connection layer having the second conductivity type, extending in another direction crossing the one direction, and connecting the base region and the electric field block layer;
a plurality of trench gate structures including:
a gate trench disposed deeper than the base region from a surface of the source region;
a gate insulation film covering an inner wall of the gate trench;
and an gate electrode disposed on the gate insulation film, and arranged in a stripe pattern along the one direction as the longitudinal direction;
an interlayer insulation film covering the gate electrode and the gate insulation film, and including a contact hole;
a source electrode electrically connected to the source region through the contact hole;
and
a drain electrode disposed on a back surface of the substrate, wherein:
a channel region is provided in a portion of the base region in contact with each trench gate structure by applying a gate voltage to the gate electrode and applying a normal operation voltage as a drain voltage to the drain electrode;
and a current flows between the source electrode and the drain electrode through the source region and the JFET portion.

16 more elements

A method for manufacturing a semiconductor device including an inversion type semiconductor element, the method comprising:

preparing a substrate made of semiconductor having a first conductivity type or a second conductivity type;
forming a drift layer, made of semiconductor having the first conductivity type with an impurity concentration lower than the substrate, on the substrate;
forming a saturation current suppression layer, including:
a plurality of electric field block layers made of semiconductor having the second conductivity type and arranged in a stripe pattern along one direction a longitudinal direction;
and a JFET portion made of semiconductor having the first conductivity type and including a plurality of portions which are arranged in a stripe pattern and alternately arranged with the electric field block layer, on the drift layer;
forming a current dispersion layer, made of semiconductor having the first conductivity type with a first conductivity type impurity concentration higher than the drift layer, on the saturation current suppression layer;
forming a base region, made of semiconductor having the second conductivity type, on the current dispersion layer;
forming a source region, made of semiconductor having the first conductivity type with the first conductivity type impurity concentration higher than the drift layer, on the base region;
forming a deep trench that penetrates the base region and the current dispersion layer from a surface of the source region, reaches the electric field block layer, and has a longitudinal direction crossing the one direction;
forming a connection layer, having the second conductivity type, and connecting the base region and the electric field block layer, in the deep trench;
forming a plurality of trench gate structures by forming a plurality of gate trenches, deeper than the base region from a surface of the source region and the connection layer, in a stripe pattern along the one direction as the longitudinal direction, then, by forming a gate insulation film on an inner wall of each gate trench, and by forming an gate electrode on the gate insulation film;
forming a source electrode electrically connected to the source region;
and
forming a drain electrode on a back surface of the substrate.

11 more elements

A method for manufacturing a semiconductor device including an inversion type semiconductor element, the method comprising:

preparing a substrate made of semiconductor having a first conductivity type or a second conductivity type;
forming a drift layer, made of semiconductor having the first conductivity type with an impurity concentration lower than the substrate, on the substrate;
forming a saturation current suppression layer, including:
a plurality of electric field block layers made of semiconductor having the second conductivity type and arranged in a stripe pattern along one direction a longitudinal direction;
and a JFET portion made of semiconductor having the first conductivity type and including a plurality of portions which are arranged in a stripe pattern and alternately arranged with the electric field block layer, on the drift layer;
forming a current dispersion layer, made of semiconductor having the first conductivity type with a first conductivity type impurity concentration higher than the drift layer, on the saturation current suppression layer;
forming a connection layer having the second conductivity type, extending in another direction crossing the one direction, and reaching the electric field block layer by ion implanting the second conductivity type impurity on the current dispersion layer;
forming a base region, made of semiconductor having the second conductivity type, on the current dispersion layer and the connection layer;
forming a source region, made of semiconductor having the first conductivity type with the first conductivity type impurity concentration higher than the drift layer, on the base region;
forming a plug layer having the second conductivity type and reaching the base region by ion implanting the second conductivity type impurity on the source region;
forming a plurality of trench gate structures by forming a plurality of gate trenches, deeper than the base region from a surface of the source region and the connection layer, in a stripe pattern along the one direction as the longitudinal direction, then, by forming a gate insulation film on an inner wall of each gate trench, and by forming an gate electrode on the gate insulation film;
forming a source electrode electrically connected to the source region;
and
forming a drain electrode on a back surface of the substrate.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/729,733Filed 30 Dec 2019 · continuation
Priority: JP 2017-1339177 Jul 2017
Published: US 2020/0161467 A121 May 2020
Granted: 31 Aug 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10D 30/668
Vertical dmos [vdmos] fets: having trench gate electrodes, e.g. UMOS transistors
H10D 84/141
Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode: vDMOS having built-in components
H10D 12/038
Of vertical IGBTs: having a recessed gate, e.g. trench-gate IGBTs
H10D 30/0297
Of vertical dmos [vdmos] fets: using recessing of the gate electrodes, e.g. to form trench gate electrodes