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US 11,107,904 B2Granted
Inner spacer formation in multi-gate transistors
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHan-Yu Lin, Chansyun David Yang, Tze-Chung Lin, Fang-Wei Lee, Fo-Ju Lin, Li-Te Lin, Pinyen Lin
Life of this patent
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Abstract
A method of fabricating a semiconductor device includes forming a structure including multiple nanowires vertically stacked above a substrate; depositing a dielectric material layer wrapping around the nanowires; performing a treatment process to a surface portion of the dielectric material layer; selectively etching the surface portion of the dielectric material layer; repeating the steps of performing the treatment process and selectively etching until the nanowires are partially exposed; and forming a gate structure engaging the nanowires.
Claims20
A method, comprising:
- forming a structure including multiple nanowires vertically stacked above a substrate;
- depositing a dielectric material layer wrapping around the nanowires;
- performing a treatment process to a surface portion of the dielectric material layer;
- selectively etching the surface portion of the dielectric material layer;
- repeating the steps of performing the treatment process and selectively etching until the nanowires are partially exposed, wherein before the nanowires are partially exposed the dielectric material layer protects the nanowires from receiving the treatment process;
- and
- forming a gate structure engaging the nanowires.
4 more elements
A method, comprising:
- forming a fin protruding from a substrate, the fin having a plurality of sacrificial layers and a plurality of channel layers, wherein the sacrificial layers and the channel layers are alternately arranged;
- removing the sacrificial layers to expose the channel layers;
- depositing a spacer material in areas from which the sacrificial layers have been removed, such that the spacer material fully wraps around the channel layers in a channel region of the fin;
- performing a surface treatment to a surface portion of the spacer material that is exposed in the channel region of the fin;
- selectively etching the surface portion of the spacer material that receives the surface treatment, thereby reducing a thickness of the spacer material in the channel region;
- while sidewalls of the channel layers remain unexposed in the channel region, repeating the steps of performing the surface treatment and selectively etching until at least a portion of the sidewalls of the channel layers are exposed, wherein a portion of the spacer material remains between the adjacent channel layers in the channel region;
- repeating the steps of performing the surface treatment and selectively etching until the portion of the spacer material between adjacent channel layers in the channel region is removed;
- and
- forming a gate structure engaging the channel layers.
6 more elements
A method, comprising:
- forming a fin including a first silicon layer, a second silicon layer, and a silicon germanium (SiGe) layer interposing between the first and second silicon layers;
- forming a dummy gate structure over a channel region of the fin;
- forming an outer spacer adjacent the dummy gate structure;
- epitaxially growing a source/drain (S/D) feature interfacing the first silicon layer, the second silicon layer, and the SiGe layer;
- removing the dummy gate structure;
- removing a portion of the SiGe layer to expose the first and second silicon layers in the channel region and in an area directly below the outer spacer;
- forming a dielectric layer wrapping around the first and second silicon layers;
- removing a first portion of the dielectric layer to partially expose the first and second silicon layers in the channel region;
- after the removing of the first portion of the dielectric layer, performing a passivation treatment to the exposed first and second silicon layers;
- after the performing of the passivation treatment, removing a second portion of the dielectric layer to provide an opening between the first and second silicon layers in the channel region, wherein a third portion of the dielectric layer remains as an inner spacer feature;
- and
- forming a gate structure in the opening between the first and second silicon layers in the channel region, wherein the inner spacer feature interposes between the S/D feature and the gate structure.
9 more elements
Dependencies are inferred from the claim text.