Charge storage memory device including ferroelectric layer between control gate electrode layers and methods of making the same

A method of forming a three-dimensional memory device, comprising:

• forming an alternating stack of insulating layers and sacrificial material layers over a substrate;
• forming memory openings through the alternating stack;
• forming memory stack structures located within a memory opening that extends through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting the memory film;
• and
• replacing the sacrificial material layers with electrode layers, wherein each of the electrode layers comprises a layer stack including a metallic barrier layer comprising a first metallic material, a ferroelectric material layer in contact with the metallic barrier layer, and a metallic fill material layer comprising a second metallic material, contacting the ferroelectric material layer, and is spaced from the metallic barrier layer by the ferroelectric material layer;
• wherein each of the memory films comprises:
• a charge storage layer deposited over a sidewall of a respective one of the memory openings;
• and
• a tunneling dielectric layer deposited on the charge storage layer, wherein one of the vertical semiconductor channels is formed on the tunneling dielectric layer.

A method of forming a three-dimensional memory device, comprising:

• forming an alternating stack of insulating layers and sacrificial material layers over a substrate;
• forming memory openings through the alternating stack;
• forming memory stack structures located within a memory opening that extends through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting the memory film, wherein the vertical semiconductor channel comprises a semiconductor material having a doping of a first conductivity type;
• forming a drain region having a doping of a second conductivity type at each top end of the vertical semiconductor channels;
• and
• replacing the sacrificial material layers with electrode layers, wherein each of the electrode layers comprises a layer stack including a metallic barrier layer comprising a first metallic material, a ferroelectric material layer in contact with the metallic barrier layer, and a metallic fill material layer comprising a second metallic material, contacting the ferroelectric material layer, and is spaced from the metallic barrier layer by the ferroelectric material layer;
• and
• forming a source region having a doping of the second conductivity type in, on, or over the substrate, wherein the source region is electrically connected to a bottom end of each of the vertical semiconductor channels.