Dual-gate transistors and their integrated circuits and preparation method thereof

A dual-gate transistor, comprising:

• an insulating substrate;
• a semiconductor layer on the insulating substrate;
• and
• at least one P-type transistor or at least one N-type transistor,
• wherein the semiconductor layer includes a plurality of channel regions separated from each other, wherein each of the plurality of channel regions is provided with a P-type transistor or an N-type transistor,
• wherein the P-type transistor includes:
• a pair of contact electrodes on the channel region, wherein one of the electrodes is a source electrode connected to VDD and the other one of the electrodes is a drain electrode,
• a gate dielectric layer between the pair of contact electrodes;
• a main gate electrode on the gate dielectric layer near the source electrode;
• and
• an auxiliary gate electrode near the drain electrode connected to GND,
• wherein the N-type transistor includes:
• a pair of contact electrodes on the channel region, wherein one of the electrodes is a source electrode connected to GND and the other one of the electrodes is a drain electrode,
• a gate dielectric layer between the pair of electrodes;
• a main gate electrode on the gate dielectric layer near the source electrode;
• and
• an auxiliary gate electrode near the drain electrode connected to VDD,
• wherein the auxiliary gate electrodes of P-type transistor and N-type transistor are respectively connected with GND and VDD.