FINFET transistor having a doped subfin structure to reduce channel to substrate leakage

A computing system, comprising:

• one or more processing cores;
• a system memory;
• a memory controller coupled to the system memory;
• a networking interface;
• a semiconductor chip comprising a FINFET transistor, said FINFET transistor comprising a channel, said channel comprising a first semiconductor material that is epitaxially grown on a subfin structure beneath the channel, the subfin structure comprising a second semiconductor material that is different than the first semiconductor material, the subfin structure in a trench in a dielectric layer, the dielectric layer having a bottom surface, and the subfin structure being epitaxially grown on a substrate comprising a third semiconductor material that is different than the first and second semiconductor materials, the subfin structure having an upper region above a doped region, the doped region to substantially impede leakage currents between the channel and the substrate, wherein the doped region has a bottom surface below the bottom surface of the dielectric layer, wherein the doped region has a top surface above the bottom surface of the dielectric layer, and wherein the doped region has a higher concentration of dopants than a concentration of dopants in the upper region of the subfin structure.