Memory device and method of fabricating the memory device

A memory device, comprising:

• a substrate;
• a first group of nanosheets vertically arranged over a first region of the substrate, wherein the first group of nanosheets comprises:
• a first semiconductor nanosheet;
• and
• a second semiconductor nanosheet over the first semiconductor nanosheet;
• a first ferroelectric layer surrounding the first semiconductor nanosheet;
• and
• a first metal gate layer surrounding the first ferroelectric layer.

A semiconductor structure, comprising:

• a substrate;
• a first group of nanosheets at a first level above the substrate, comprising:
• a first semiconductor nanosheet over a first region;
• a second semiconductor nanosheet over a second region adjacent to the first region;
• and
• a first gate layer at least partially surrounding the first semiconductor nanosheet and the second semiconductor nanosheet;
• a second group of nanosheets at a second level above the first level, comprising:
• a third semiconductor nanosheet over the first region;
• and
• a conductive via over the second region, wherein the conductive via is connected to a top surface of the first gate layer.