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US 11,107,843 B2Granted
Array substrate, manufacturing method thereof, and display panel
AssigneesBoe Technology Group Co., Ltd., Beijing Boe Display Technology Co., Ltd.
InventorsLianjie Qu, Bingqiang Gui, Yonglian Qi, Hebin Zhao, Yun Qiu, Dan Wang
Life of this patent
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Abstract
An array substrate includes a substrate, a dual-gate oxide thin film transistor TFT, an electrode for display and a polycrystalline silicon TFT. The dual-gate oxide thin film transistor TFT and the electrode for display are located in a sub-pixel on the substrate, and a drain electrode of the dual-gate oxide TFT is electrically connected to the electrode for display.
Claims12
An array substrate, comprising:
- a substrate;
- a dual-gate oxide thin film transistor (TFT) located in a sub-pixel on the substrate and an electrode for display, wherein, a drain electrode of the dual-gate oxide TFT is electrically connected to the electrode for display;
- and
- a polycrystalline silicon TFT located on the substrate;
- wherein,
- the polycrystalline silicon TFT comprises a polycrystalline silicon active layer, a gate insulation layer, a gate electrode, at least one interlayer insulation laver, a source electrode and a drain electrode, which are sequentially arranged on the substrate, and the source electrode and the drain electrode of the polycrystalline silicon TFT are in contact with the polycrystalline silicon active layer through two first through holes, respectively, the two first through holes being provided in the gate insulation layer and the at least one interlayer insulation layer,
- a bottom-gate electrode of the dual-gate oxide TFT and the gate electrode of the polycrystalline silicon TFT are formed synchronously;
- the at least one interlayer insulation layer comprises a first interlayer insulation sub-layer and a second interlayer insulation sub-layer, and the second interlayer insulation sub-layer is located on a side of the first interlayer insulation sub-layer away from the substrate,
- the first interlayer insulation sub-layer and the second interlayer insulation sub-layer cover the bottom-gate electrode, and
- an oxide semiconductor active layer of the dual-gate oxide TFT is located between the first interlayer insulation sub-layer and the second interlayer insulation sub-layer.
7 more elements
Dependencies are inferred from the claim text.