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US 11,107,833 B2Granted
Semiconductor devices
AssigneeSamsung Electronics Co., Ltd.
InventorsChanghyun Lee, Chanjin Park, Byoungkeun Son, Sung-Il Chang
Life of this patent
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Abstract
A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.
Claims17
A semiconductor device, comprising:
- a semiconductor layer;
- an underlying layer disposed on the semiconductor layer, and including a plurality of layers;
- a stack structure disposed on the underlying layer;
- an opening penetrating the stack structure and extending into the underlying layer toward a bottom surface of the underlying layer;
- an insulating spacer disposed on an inner wall of the opening;
- a recessed hole disposed at a lower end of the opening and exposing a portion of the semiconductor layer and a portion of the underlying layer;
- a semiconductor pattern covering the insulating spacer in the opening and directly contacting an inner wall of the recessed hole;
- and
- a gap-filling pattern in an inner space of the semiconductor pattern,
- wherein a bottom surface of the insulating spacer is positioned at a vertical level between a top surface and the bottom surface of the underlying layer, and the bottom surface of the insulating spacer is spaced apart from a top surface of the semiconductor layer,
- wherein the plurality of layers includes a first layer and a second layer on the first layer, the first layer containing silicon oxide, and the second layer containing aluminum oxide,
- wherein the insulating spacer extends toward the first layer along the inner wall of the opening, and
- wherein a bottom surface of the gap-filling pattern is positioned at a vertical level lower than the bottom surface of the underlying layer and higher than a bottom surface of the semiconductor pattern.
10 more elements
A semiconductor device, comprising:
- a semiconductor layer;
- an underlying layer disposed on the semiconductor layer, and including a plurality of layers that are stacked;
- a stack structure disposed on the underlying layer;
- and
- a channel structure penetrating the stack structure,
- wherein the channel structure includes:
- a semiconductor pattern penetrating the stack structure and the underlying layer and contacting the semiconductor layer;
- an insulating spacer disposed on a sidewall of the semiconductor pattern;
- and
- a gap-filling pattern in an inner space of the semiconductor pattern,
- wherein a bottom surface of the insulating spacer is positioned at a vertical level between a top surface and a bottom surface of the underlying layer,
- wherein a bottom surface of the semiconductor pattern is positioned at a vertical level lower than the bottom surface of the underlying layer,
- wherein the plurality of layers includes a first layer and a second layer on the first layer, the first layer containing silicon oxide, and the second layer containing aluminum oxide,
- wherein the insulating spacer extends toward the first layer along the sidewall of the semiconductor pattern, and
- wherein a bottom surface of the gap-filling pattern is positioned at a vertical level lower than the bottom surface of the underlying layer and higher than the bottom surface of the semiconductor pattern.
12 more elements
A semiconductor device, comprising:
- a semiconductor layer;
- an underlying layer disposed on the semiconductor layer, and including a plurality of layers that are stacked;
- a first structure disposed on the underlying layer, and including three-dimensionally arranged memory devices;
- a second structure disposed on the first structure, and including a conductive pattern;
- a first semiconductor pattern penetrating the first structure;
- a second semiconductor pattern penetrating the second structure;
- and
- a pad pattern disposed between the first structure and the second structure,
- wherein the first structure and the second structure are electrically connected to each other via the first semiconductor pattern and the second semiconductor pattern,
- a lower end of the second semiconductor pattern is disposed on and proximal to an upper end of the first semiconductor pattern,
- a lower end of the first semiconductor pattern is in contact with the semiconductor layer,
- an upper end of the second semiconductor pattern is electrically connected to a bit line, and
- a bottom surface of the second semiconductor pattern is located at a vertical level between a top surface and a bottom surface of the pad pattern.
10 more elements
Dependencies are inferred from the claim text.