Integrated assemblies having vertically-spaced channel material segments, and methods of forming integrated assemblies

A NAND memory array, comprising:

• a vertical stack of alternating insulative levels and conductive levels;
• the conductive levels including control gate regions and second regions proximate the control gate regions;
• high-k dielectric structures directly against the control gate regions and extending entirely across the insulative levels;
• charge-blocking material adjacent the high-k dielectric structures;
• charge-storage material adjacent the charge-blocking material;
• the charge-storage material being configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another;
• gate-dielectric material adjacent the charge-storage material;
• channel material extending vertically along the stack and being adjacent the gate-dielectric material;
• and
• wherein at least portions of the high-k dielectric structures comprise a laminate of two or more different high-k dielectric materials.

An integrated structure, comprising:

• a vertical stack of alternating insulative levels and conductive levels;
• the conductive levels having terminal regions, and having nonterminal regions proximate the terminal regions;
• high-k dielectric material adjacent the terminal regions and extending vertically across the insulative levels;
• charge-blocking material adjacent the terminal regions;
• charge-storage material arranged in vertically-stacked spaced-apart segments;
• the segments being adjacent the charge-blocking material;
• gate-dielectric material adjacent the charge-storage material;
• and
• channel material adjacent the gate-dielectric material;
• and
• wherein the high-k dielectric material is adjacent to the terminal regions and is not along the nonterminal regions;
• wherein the terminal regions have top surfaces and bottom surfaces, and have vertically-extending sidewall surfaces between the top surfaces and the bottom surfaces;
• wherein the high-k dielectric material extends along the top surfaces and the bottom surfaces of the terminal regions, and not along the sidewall surfaces of the terminal regions;
• and wherein the high-k dielectric material is a first high-k dielectric material;
• and further comprising a second high-k dielectric material between the first high-k dielectric material and the conductive levels;
• the second high-k dielectric material wrapping around the terminal regions and extending along the nonterminal regions;
• the second high-k dielectric material being of a different composition than the first high-k dielectric material.

An integrated structure, comprising:

• a vertical stack of alternating insulative levels and conductive levels;
• the conductive levels having terminal regions, and having nonterminal regions proximate the terminal regions;
• high-k dielectric material adjacent the terminal regions and extending vertically across the insulative levels;
• charge-blocking material adjacent the terminal regions;
• charge-storage material arranged in vertically-stacked spaced-apart segments;
• the segments being adjacent the charge-blocking material;
• gate-dielectric material adjacent the charge-storage material;
• and
• channel material adjacent the gate-dielectric material;
• and
• wherein the high-k dielectric material wraps around the terminal regions;
• wherein the terminal regions have top surfaces and bottom surfaces, and have vertically-extending sidewall surfaces between the top surfaces and the bottom surfaces;
• wherein the high-k dielectric material extends along the top surfaces, the bottom surfaces and the sidewall surfaces of the terminal regions, and is a first high-k dielectric material;
• wherein the first high-k dielectric material is not along the nonterminal regions;
• and further comprising a second high-k dielectric material between the first high-k dielectric material and the conductive levels;
• the second high-k dielectric material wrapping around the terminal regions and extending along the nonterminal regions;
• the second high-k dielectric material being of a different composition than the first high-k dielectric material.

An integrated structure, comprising:

• a vertical stack of alternating insulative levels and conductive levels;
• the conductive levels having terminal regions, and having nonterminal regions proximate the terminal regions;
• high-k dielectric material adjacent the terminal regions and extending vertically across the insulative levels;
• charge-blocking material adjacent the terminal regions;
• charge-storage material arranged in vertically-stacked spaced-apart segments;
• the segments being adjacent the charge-blocking material and laterally spaced from the conductive levels, a portion of the segments extending past the conductive levels to be laterally spaced from the insulative levels;
• gate-dielectric material adjacent the charge-storage material;
• channel material adjacent the gate-dielectric material;
• and
• wherein the high-k dielectric material is adjacent to the terminal regions and is not along the nonterminal regions;
• wherein the terminal regions have top surfaces and bottom surfaces, and have vertically-extending sidewall surfaces between the top surfaces and the bottom surfaces;
• wherein the high-k dielectric material extends along the top surfaces and the bottom surfaces of the terminal regions, and not along the sidewall surfaces of the terminal regions;
• and wherein the high-k dielectric material is a first high-k dielectric material;
• and further comprising a second high-k dielectric material between the first high-k dielectric material and the conductive levels;
• the second high-k dielectric material wrapping around the terminal regions and extending along the nonterminal regions;
• the second high-k dielectric material being of a different composition than the first high-k dielectric material.

An integrated structure, comprising:

• a vertical stack of alternating insulative levels and conductive levels;
• the conductive levels having terminal regions, and having nonterminal regions proximate the terminal regions;
• high-k dielectric material adjacent the terminal regions and extending vertically across the insulative levels;
• charge-blocking material adjacent the terminal regions;
• charge-storage material arranged in vertically-stacked spaced-apart segments;
• the segments being adjacent the charge-blocking material and laterally spaced from the conductive levels, a portion of the segments extending past the conductive levels to be laterally spaced from the insulative levels;
• gate-dielectric material adjacent the charge-storage material;
• channel material adjacent the gate-dielectric material;
• and
• wherein the high-k dielectric material wraps around the terminal regions;
• wherein the terminal regions have top surfaces and bottom surfaces, and have vertically-extending sidewall surfaces between the top surfaces and the bottom surfaces;
• wherein the high-k dielectric material extends along the top surfaces, the bottom surfaces and the sidewall surfaces of the terminal regions, and is a first high-k dielectric material;
• wherein the first high-k dielectric material is not along the nonterminal regions;
• and further comprising a second high-k dielectric material between the first high-k dielectric material and the conductive levels;
• the second high-k dielectric material wrapping around the terminal regions and extending along the nonterminal regions;
• the second high-k dielectric material being of a different composition than the first high-k dielectric material.

An integrated structure, comprising:

• a vertical stack of alternating insulative levels and conductive levels;
• the conductive levels having terminal regions, and having nonterminal regions proximate the terminal regions;
• high-k dielectric material adjacent the terminal regions and extending vertically across the insulative levels;
• charge-blocking material adjacent the terminal regions;
• charge-storage material arranged in vertically-stacked spaced-apart segments;
• the segments being adjacent the charge-blocking material and laterally spaced from the conductive levels, a portion of the segments extending past the conductive levels to be laterally spaced from the insulative levels;
• gate-dielectric material adjacent the charge-storage material;
• channel material adjacent the gate-dielectric material;
• and
• wherein the high-k dielectric material wraps around the terminal regions;
• wherein the terminal regions have top surfaces and bottom surfaces, and have vertically-extending sidewall surfaces between the top surfaces and the bottom surfaces;
• and wherein the high-k dielectric material extends along the top surfaces, the bottom surfaces and the sidewall surfaces of the terminal regions, and is not along the nonterminal regions.

An integrated structure, comprising:

• a vertical stack of alternating insulative levels and conductive levels;
• the conductive levels having terminal regions, and having nonterminal regions proximate the terminal regions;
• high-k dielectric material adjacent the terminal regions and extending vertically across the insulative levels;
• charge-blocking material adjacent the terminal regions;
• charge-storage material arranged in vertically-stacked spaced-apart segments;
• the segments being adjacent the charge-blocking material and laterally spaced from the conductive levels, a portion of the segments extending past the conductive levels to be laterally spaced from the insulative levels;
• gate-dielectric material adjacent the charge-storage material;
• channel material adjacent the gate-dielectric material;
• and
• wherein at least portions of the high-k dielectric material comprise a laminate of two or more different high-k dielectric materials.

A NAND memory array, comprising:

• a vertical stack of alternating insulative levels and conductive levels;
• the conductive levels including control gate regions and second regions proximate the control gate regions;
• high-k dielectric structures directly against the control gate regions and extending entirely across the insulative levels;
• charge-blocking material adjacent the high-k dielectric structures;
• charge-storage material adjacent the charge-blocking material;
• the charge-storage material being configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another;
• gate-dielectric material adjacent the charge-storage material;
• channel material extending vertically along the stack and being adjacent the gate-dielectric material;
• and
• wherein the segments of the charge-storage material are laterally spaced from the conductive levels and a portion of the segments extend past the conductive levels to be laterally spaced from the insulative levels.