Method of manufacturing a three-dimensional non-volatile memory device
AssigneeSK hynix Inc.
InventorsEun Mee Kwon, Da Som Lee
Life of this patent
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Abstract
In a method of manufacturing a non-volatile memory device, insulating layers and conductive gates may be alternately formed on a semiconductor substrate to form a stack structure. A contact hole may be formed through the stack structure. A channel layer may be formed on a surface of the contact hole. The contact hole may be filled with a gap-fill insulating layer. The gap-fill insulating layer may be etched by a target depth to define a preliminary junction region. The channel layer may be etched until a surface of the channel layer may correspond to a surface of an uppermost gate among the gates. Diffusion-preventing ions may be implanted into the channel layer. A capping layer with impurities may be formed in the preliminary junction region.
Claims19
A method of manufacturing a non-volatile memory device, the method comprising:
- forming a stack structure in which an insulating layer and a sacrificial layer are alternately stacked two or more times, wherein the stack structure includes a plurality of insulating layers and a plurality of sacrificial layers;
- forming a contact hole through the stack structure;
- forming a channel layer on an inner surface of the contact hole;
- filling the contact hole with a gap-fill insulating layer;
- selectively removing the sacrificial layers to form a plurality of spaces;
- forming conductive layers in each of the plurality of spaces to form a plurality of conductive gates, positioned between the insulating layers;
- etching the gap-fill insulating layer by a target depth to form a preliminary junction region;
- etching a portion of the channel layer, to provide the channel layer with a top surface substantially coplanar corresponding to a top surface of an uppermost gate among the gates;
- implanting diffusion-preventing ions into a selected portion of the channel layer;
- and
- forming a capping layer with conductive impurities in the preliminary junction region to form a junction region.
A method of manufacturing a non-volatile memory device, the method comprising:
- forming a stack structure in which an insulating layer and a sacrificial layer are alternately stacked two or more times, wherein the stack structure includes a plurality of insulating layers and a plurality of sacrificial layers;
- forming a contact hole through the stack structure;
- forming a channel layer on an inner surface of the contact hole;
- filling the contact hole with a gap-fill insulating layer;
- selectively removing the sacrificial layers to form a plurality of spaces;
- forming conductive layers in each of the plurality of spaces to form a plurality of conductive gates, positioned between the insulating layers;
- etching the gap-fill insulating layer to a depth shallower than a target depth to define a preliminary junction region;
- implanting impurities into a portion of the channel layer to form a junction extension region that has a bottom surface substantially coplanar with a top surface of an uppermost gate among the conductive gates;
- and
- forming a capping layer with conductive impurities in the preliminary junction region.
Dependencies are inferred from the claim text.