Integration of split gate metal-oxide-nitride-oxide-semiconductor memory with vertical FET
AssigneeInternational Business Machines Corporation
InventorsRuilong Xie, Julien Frougier, Kangguo Cheng
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Abstract
Embodiments of the present invention are directed to techniques for integrating a split gate metal-oxide-nitride-oxide-semiconductor (SG-MONOS) memory with a vertical field effect transistor (VFET). In a non-limiting embodiment of the invention, a vertical SG-MONOS memory device is formed on a first region of a substrate. The SG-MONOS memory device can include a charge storage stack, a memory gate on the charge storage stack, and a control gate vertically stacked over the charge storage stack and the memory gate. A VFET is formed on a second region of the substrate. The VFET can include a logic gate.
Claims14
A method for forming a semiconductor device, the method comprising:
- forming a vertical split gate metal-oxide-nitride-oxide-semiconductor (SG-MONOS) memory device on a first region of a substrate, wherein forming the SG-MONOS memory device comprises:
- forming a charge storage stack;
- forming a memory gate on the charge storage stack;
- and
- forming a control gate vertically stacked over the charge storage stack and the memory gate;
- and
- forming a vertical field effect transistor (VFET) on a second region of the substrate, the VFET comprising a logic gate;
- wherein a first cavity in the first region of the substrate is formed in parallel with a second cavity in the second region of the substrate, the first cavity defining a buried contact region of the SG-MONOS and the second cavity defining a shallow trench isolation region of the VFET.
A method for forming a semiconductor device, the method comprising:
- forming a first semiconductor fin on a substrate;
- forming a second semiconductor fin on the substrate;
- forming a charge storage stack on a sidewall of the first semiconductor fin, the charge storage stack comprising a tunneling oxide layer, an insulating oxide layer, and a charge storage layer between the tunneling oxide layer and the insulating oxide layer;
- forming a memory gate on the charge storage stack;
- forming a control gate vertically stacked over the charge storage stack and the memory gate, the control gate on the sidewall of the first semiconductor fin;
- and
- forming a logic gate on a sidewall of the second semiconductor fin;
- wherein a first cavity in a first region of the substrate is formed in parallel with a second cavity in a second region of the substrate, the first cavity defining a buried contact region of a split gate metal-oxide-nitride-oxide-semiconductor (SG-MONOS) memory device and the second cavity defining a shallow trench isolation region of a vertical field effect transistor (VFET).
Dependencies are inferred from the claim text.