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US 11,107,826 B2Granted
Semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsHae-min Lee, Kwang-soo Kim, Sun-il Shim
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Abstract
A semiconductor memory device includes gate electrodes arranged on a substrate to be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, an upper insulation layer arranged on an uppermost gate electrode, channel structures penetrating through the upper insulation layer, and the gate electrodes in the first direction, and string selection line cut insulation layers horizontally separating the upper insulation layer and the uppermost gate electrode. Each of the string selection line cut insulation layers includes a protrusion protruding toward the uppermost gate electrode and positioning on the same level as the first gate electrode.
Claims20
A semiconductor memory device comprising:
- a plurality of gate electrodes arranged on a substrate to be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate;
- a plurality of insulation layers arranged between the plurality of gate electrodes;
- an upper insulation layer arranged on an uppermost gate electrode of the plurality of gate electrodes, wherein the upper insulation layer is positioned higher than the uppermost gate electrode from an upper surface of the substrate;
- a plurality of channel structures penetrating through the upper insulation layer, the plurality of gate electrodes, and the plurality of insulation layers in the first direction, each of the plurality of channel structures including a plurality of layers;
- and
- a plurality of string selection line cut insulation layers horizontally separating each of the upper insulation layer and the uppermost gate electrode into discrete portions not in contact with one another, such that the discrete portions include a separated uppermost gate electrode and a separated upper insulation layer,
- wherein each of the plurality of string selection line cut insulation layers includes a first body portion penetrating the upper insulation layer and the uppermost gate electrode, and a first protrusion protruding from a sidewall of the first body portion toward the separated uppermost gate electrode and positioned at the same level as the separated uppermost gate electrode.
4 more elements
A semiconductor memory device comprising:
- a plurality of gate electrodes arranged on a substrate to be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate;
- a plurality of insulation layers arranged between the plurality of gate electrodes;
- an upper insulation layer arranged on a first gate electrode, which is an uppermost gate electrode of the plurality of gate electrodes;
- a plurality of channel structures penetrating through the upper insulation layer, the plurality of gate electrodes, and the plurality of insulation layers in the first direction, each of the plurality of channel structures including a plurality of layers;
- a pair of word line cuts separating each gate electrode of the plurality of gate electrodes and separating each insulation layer of the plurality of insulation layers in a second direction parallel to the upper surface of the substrate;
- and
- a plurality of string selection line cut insulation layers arranged between the pair of word line cuts and separating the upper insulation layer in the second direction to form a separated upper insulation layer and separating the first gate electrode in the second direction to form a separated first gate electrode,
- wherein each of the plurality of string selection line cut insulation layers includes a sidewall spaced apart from a sidewall of the separated upper insulation layer.
5 more elements
A semiconductor memory device comprising:
- a plurality of gate electrodes arranged on a substrate to be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, and each of the plurality of gate electrodes comprising a gate conductive layer and a first barrier layer covering the gate conductive layer, each of the plurality of gate electrodes comprising:
- at least one ground selection gate electrode arranged on the substrate,
- a plurality of word line gate electrodes arranged on the at least one ground selection gate electrode, and
- at least one string selection gate electrode arranged on the plurality of word line gate electrodes;
- a plurality of insulation layers arranged between the plurality of gate electrodes;
- an upper insulation layer arranged on the at least one string selection gate electrode;
- a plurality of channel structures penetrating through the upper insulation layer, the plurality of gate electrodes, and the plurality of insulation layers in the first direction, each of the plurality of channel structures including a plurality of layers;
- a pair of word line cut insulation layers, wherein the plurality of gate electrodes and the plurality of insulation layers are disposed between the pair of the word line cut insulation layers spaced apart from each other in a second direction parallel to the upper surface of the substrate;
- and
- a plurality of string selection line cut insulation layers arranged between the pair of word line cut insulation layers and separating horizontally each of the upper insulation layer and the at least one string selection gate electrode into discrete portions not in contact with one another in the second direction,
- wherein a portion of the first barrier layer included in the at least one string selection gate electrode is between the upper insulation layer and each of the plurality of the string selection line cut insulation layers.
8 more elements
Dependencies are inferred from the claim text.