Semiconductor device

A semiconductor device comprising:

• a first fin type pattern which extends lengthwise in a first direction and has a first width in a second direction different from the first direction, in a first SRAM region;
• a second fin type pattern which extends lengthwise in the first direction and is spaced apart from the first fin type pattern in the second direction, in the first SRAM region;
• first to fourth gate patterns which intersect the first fin type pattern and are disposed sequentially in the first direction, each of the first gate pattern and the fourth gate pattern further intersecting the second fin type pattern;
• a first semiconductor pattern disposed on the first fin type pattern and between the second gate pattern and the third gate pattern;
• a second semiconductor pattern disposed on the second fin type pattern corresponding to the first semiconductor pattern, the second semiconductor pattern and the first semiconductor pattern being spaced apart from each other in the second direction;
• a third fin type pattern which extends lengthwise in a third direction and has a second width in a fourth direction different from the third direction, in a second SRAM region;
• fourth and fifth fin type patterns which extend lengthwise in the third direction in the second SRAM region and are spaced apart from the third fin type pattern in the fourth direction, the fourth and fifth fin type patterns being arranged in the third direction;
• fifth to eighth gate patterns which intersect the third fin type pattern and are sequentially arranged in the third direction, the fifth gate pattern further intersecting the fourth fin type pattern, and the eighth gate pattern further intersecting the fifth fin type pattern;
• a third semiconductor pattern disposed on the third fin type pattern and between the sixth gate pattern and the seventh gate pattern;
• and
• a field insulating film disposed between a short side of the fourth fin type pattern and a short side of the fifth fin type pattern,
• wherein an extension line passing through the third semiconductor pattern and extending in the fourth direction passes between the fourth fin type pattern and the fifth fin type pattern.

A semiconductor device comprising:

• a first fin type pattern disposed in an SRAM region;
• a plurality of semiconductor patterns disposed on the first fin type pattern to be spaced apart from each other in a first direction, and divided into a first group and a second group;
• a plurality of nanosheet structures, each having at least one or more nanosheets and being disposed between corresponding two adjacent semiconductor patterns of the plurality of semiconductor patterns;
• and
• a plurality of gate patterns, each being disposed on a corresponding one of the plurality of nanosheet structures,
• wherein the semiconductor patterns of the first group are electrically connected to a plurality of wiring structures,
• wherein the semiconductor patterns of the second group are configured to be electrically floating, and
• wherein the plurality of wiring structures include a first wiring structure which is connected to a corresponding semiconductor pattern of the plurality of semiconductor patterns of the first group and a corresponding gate pattern of the plurality of gate patterns, and vertically overlaps the corresponding gate pattern.