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US 11,107,815 B2Granted
Semiconductor device
AssigneeSamsung Electronics Co., Ltd.
InventorsSungmin Kim, Dongwon Kim
Life of this patent
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Abstract
A semiconductor device includes: channel patterns disposed on a substrate; a pair of source/drain patterns disposed at first and second sides of each of the channel patterns; and a gate electrode disposed around the channel patterns, wherein the gate electrode includes a first recessed top surface between adjacent channel patterns, wherein the channel patterns are spaced apart from the substrate, and wherein the gate electrode is disposed between the substrate and the channel patterns.
Claims20
A semiconductor device, comprising:
- an active pattern on a substrate, the active pattern including:
- a first semiconductor pattern;
- and a second semiconductor pattern vertically spaced apart from the first semiconductor pattern;
- and
- a gate electrode intersecting the active pattern and extending in a first direction,
- wherein the second semiconductor pattern includes a channel pattern and a source/drain pattern on a side of the channel pattern,
- wherein at least a portion of the gate electrode is between the first semiconductor pattern and the channel pattern, and
- wherein the gate electrode includes a recessed top surface adjacent to the channel pattern.
5 more elements
A semiconductor device, comprising:
- a substrate including a PMOSFET region and a NMOSFET region;
- a first active pattern on the PMOSFET region and a second active pattern on the NMOSFET region;
- a gate electrode on the first and second active pattern patterns;
- and
- a gate capping pattern on the gate electrode,
- wherein the first active pattern includes a first channel pattern and a second channel pattern vertically spaced apart from the first channel pattern,
- wherein the second active pattern includes a third channel pattern and a fourth channel pattern vertically spaced apart from the third channel pattern,
- wherein a first portion of the gate electrode is between the first and second channel patterns,
- wherein a second portion of the gate electrode is between the third and fourth channel patterns, and
- wherein an interface where the gate electrode meets the gate capping pattern is recessed between the second channel pattern and the fourth channel pattern.
7 more elements
A semiconductor device, comprising:
- a substrate;
- a first active pattern and a second active pattern on the substrate;
- a gate electrode on the first and second active pattern patterns;
- and
- a gate capping pattern on the gate electrode,
- wherein each of the first and second active patterns includes a plurality of channel patterns that are vertically stacked and vertically spaced from each other,
- wherein the gate electrode surrounds the plurality of channel patterns of each of the first and second active patterns, and
- wherein an interface where the gate electrode meets the gate capping pattern is recessed between the first active pattern and the second active pattern.
5 more elements
Dependencies are inferred from the claim text.