US 11,107,814 B2 · Vertical fin field effect transistor devices with a replacement metal gate

Abstract

A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins. The method further includes forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates, and removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins. The method further includes forming a fill layer between adjacent pairs of the vertical fins. The method further includes removing a portion of the dummy gate layer from between the fill layer and the vertical fins, and forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.

Claims20

Dependent claims

A fin field effect transistor complementary metal oxide semiconductor (CMOS) device, comprising:

a bottom source/drain layer on a substrate;
a plurality of vertical fins in a first subset and a plurality of vertical fins in a second subset on the bottom source/drain layer;
a gate dielectric layer on each of the plurality of vertical fins in the first subset and each of the plurality of vertical fins in the second subset;
a first replacement work function material on the gate dielectric layer on the plurality of vertical fins in the first subset;
a second replacement work function layer on the gate dielectric layer on the plurality of vertical fins in the second subset, wherein the second replacement work function layer is a different work function material from the first replacement work function material;
a sidewall spacer on the first replacement work function material and gate dielectric layer on the plurality of vertical fins in the first subset;
an n-doped top source/drain on each of the plurality of vertical fins in the first subset;
and
a p-doped top source/drain on each of the plurality of vertical fins in the second subset.

6 more elements

A fin field effect transistor complementary metal oxide semiconductor (CMOS) device, comprising:

a bottom source/drain layer on a substrate;
a plurality of vertical fins in a first subset and a plurality of vertical fins in a second subset on the bottom source/drain layer;
an isolation region through the bottom source/drain layer and in the substrate that electrically separates the bottom source/drain layer into different segments below the plurality of vertical fins in the first subset and the plurality of vertical fins in the second subset;
a gate dielectric layer on each of the plurality of vertical fins in the first subset and each of the plurality of vertical fins in the second subset;
a work function layer on the gate dielectric layer on the plurality of vertical fins in the second subset;
a first replacement work function material on the gate dielectric layer on the plurality of vertical fins in the first subset;
a second replacement work function material on the gate dielectric layer on the plurality of vertical fins in the second subset, wherein the second replacement work function material is a different work function material from the first replacement work function material;
and
an n-doped top source/drain on each of the plurality of vertical fins in the first subset;
and
a p-doped top source/drain on each of the plurality of vertical fins in the second subset.

8 more elements

Dependencies are inferred from the claim text.

Vertical fin field effect transistor devices with a replacement metal gate

Life of this patent

Vertical fin field effect transistor devices with a replacement metal gate

Life of this patent

Abstract

Claims20