Metallization structures under a semiconductor device layer
AssigneeIntel Corporation
InventorsAaron D. Lilak, Rishabh Mehandru, Patrick Morrow, Stephen M. Cea
Life of this patent
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Abstract
Metallization structures under a semiconductor device layer. A metallization structure in alignment with semiconductor fin may be on a side of the fin opposite a gate stack. Backside and/or frontside substrate processing techniques may be employed to form such metallization structures on a bottom of a semiconductor fin or between bottom portions of two adjacent fins. Such metallization structures may accompany interconnect metallization layers that are over a gate stack, for example to increase metallization layer density for a given number of semiconductor device layers.
Claims14
A transistor structure, comprising:
- a first fin comprising a semiconductor material, the first fin having a top opposite a bottom with a sidewall therebetween, wherein the bottom of the first fin has a first length and a first width;
- isolation comprising a dielectric material, wherein, over at least the first length, the isolation has a second width extending between the bottom of the first fin and a bottom of a second fin;
- one or more transistor terminals over the top or the sidewall of the first fin;
- and
- a metallization structure having at least the first length, wherein:
- the metallization structure has approximately the first width and is in contact with the bottom of the first fin, and wherein the second width of the isolation is between the metallization structure and an adjacent metallization structure;
- or
- the metallization structure has approximately the second width, is in contact with the isolation, and is separated from the adjacent metallization structure by approximately the first width.
A transistor structure, comprising:
- a first fin comprising a semiconductor material, the first fin having a top opposite a bottom with a sidewall of a first height therebetween, wherein the bottom of the first fin has a first length and a first width;
- isolation comprising a dielectric material, wherein, over at least the first length, the isolation has a second width extending between the bottom of the first fin and a bottom of a second fin;
- a gate stack comprising a gate electrode and a gate dielectric, the gate stack extending over a second height of the sidewall, less than the first height;
- a source and a drain coupled to the fin on opposite sides of the gate stack;
- and
- a metallization structure having at least the first length and separated from the gate electrode by third height of the sidewall, the third height equal to a difference between the first and second heights;
- and wherein:
- the metallization structure has approximately the first width, is in contact with the bottom of the first fin, and is separated from an adjacent metallization structure by approximately the second width;
- or
- the metallization structure has at least the first length, is in contact with the isolation, and is separated from the adjacent metallization structure by approximately the first width.
Dependencies are inferred from the claim text.