Electrostatic discharge protection circuit
AssigneeTexas Instruments Incorporated
InventorsKrishna Praveen Mysore Rajagopal, Mariano Dissegna
Life of this patent
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Abstract
Described examples include an integrated circuit includes a protected node and a first transistor having a source coupled to the protected node, a gate and a drain coupled to a ground, wherein the first transistor is a MOSFET transistor. The integrated circuit also includes a second transistor having a first current handling terminal coupled to the protected node, a second current handling terminal coupled to the ground and a control terminal coupled to a reference potential, where the second transistor is configured to be off when a first voltage on the control terminal of the second transistor is less than a second voltage on the first current handling terminal of the second transistor.
Claims18
An integrated circuit comprising:
- a protected node;
- a first transistor having a drain coupled to the protected node, a gate, and a source coupled to a ground, wherein the first transistor is a MOSFET transistor;
- and
- a junction field-effect transistor (JFET) having a first current handling terminal coupled to the protected node, a second current handling terminal coupled to the gate of the first transistor, and a control terminal coupled to a reference potential, wherein the JFET is configured to be off when a first voltage on the control terminal of the second transistor is less than a second voltage on the first current handling terminal of the second transistor.
An integrated circuit comprising:
- a protected node;
- a first transistor having a source coupled to the protected node, a gate, and a drain coupled to a ground, wherein the first transistor is a MOSFET transistor;
- a resistor having a first terminal coupled to the gate of the first transistor and a second terminal coupled to the ground;
- and
- a junction field effect transistor (JFET) having a first current handling terminal coupled to the protected node, a second current handling terminal coupled the first terminal of the resistor, and a control terminal coupled to a reference potential, wherein the JFET is configured to be off when a first voltage on the control terminal of the JFET is less than a second voltage on the first current handling terminal of the JFET.
An integrated circuit comprising:
- a MOSFET transistor having a first gate, a first drain conductively connected to a protected node, and a first source;
- and
- a junction field-effect transistor (JFET) having a second gate, a second drain conductively connected to the protected node, and a second source conductively connected to the first gate;
- and
- a resistor having a first terminal conductively connected to the second drain and a second terminal conductively connected to the first source.
Dependencies are inferred from the claim text.