Method to construct 3D devices and systems

A method to construct a 3D system, the method comprising:

• providing a base wafer;
• and then
• transferring a memory control on top of said base wafer;
• and then
• thinning said memory control wafer;
• transferring a first memory wafer on top of said memory control wafer;
• and then
• thinning said first memory wafer;
• and then
• transferring a second memory wafer on top of said first memory wafer;
• and then
• thinning said second memory wafer.

A 3D device, the device comprising:

• a first stratum comprising first bit-cell memory arrays;
• a second stratum comprising second bit-cell memory arrays;
• and
• a third stratum,
• wherein said second stratum overlays said first stratum,
• wherein said first stratum overlays said third stratum,
• wherein said third stratum comprises a plurality of word-line decoders to control said first bit-cell memory arrays and said second bit-cell memory arrays;
• a logic stratum;
• and
• a thermal isolation layer disposed between said logic stratum and said first stratum,
• wherein said thermal isolation layer is designed so during said 3D device operation a first temperature of said first stratum is at least 20° C. lower than a second temperature of said logic stratum.

A 3D device, the device comprising:

• a first stratum comprising first bit-cell memory arrays;
• a second stratum comprising second bit-cell memory arrays;
• and
• a third stratum,
• wherein said second stratum overlays said first stratum,
• wherein said first stratum overlays said third stratum,
• wherein said third stratum comprises a plurality of word-line decoders to control said first bit-cell memory arrays and said second bit-cell memory arrays,
• wherein said first stratum comprises a first word-line controlling at least one of said first bit-cell memory arrays,
• wherein said second stratum comprises a second word-line, overlaying said first word-line, controlling at least one of said second bit-cell memory arrays, and
• wherein said third stratum comprises a control circuit to enable use of said second word-line as an alternative to said first word-line or use of said first word-line as an alternative to said second word-line.

A 3D device, the device comprising:

• a first stratum comprising first bit-cell memory arrays;
• a second stratum comprising second bit-cell memory arrays;
• and
• a third stratum,
• wherein said second stratum overlays said first stratum,
• wherein said first stratum overlays said third stratum,
• wherein said third stratum comprises a plurality of word-line decoders to control said first bit-cell memory arrays and said second bit-cell memory arrays,
• wherein at least one of said first stratum, said second stratum, and said third stratum comprises one or more transistors interconnected by metal layers,
• wherein a single-crystal region comprises said one or more transistors, and
• wherein said single-crystal region has a planar size greater than 40×40 mm2.