Semiconductor module including memory stack having TSVs
AssigneeSK hynix Inc.
InventorsMyoung-Seo Kim, Seung-Yong Lee, Young-Pyo Joo
Life of this patent
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Abstract
A semiconductor module includes a module board, an interposer on the module board, and a processing device and a memory stack that are disposed side by side on the interposer, wherein the memory stack includes a base die, and a memory die on the base die, wherein the memory die includes an outer bank region, a central TSV region, first and second inner bank regions, and a first non-central TSV region, wherein the central TSV region is disposed between the outer bank region and the second inner bank region, and the first non-central TSV region is disposed between the first inner bank region and the second inner bank region.
Claims27
A semiconductor module comprising:
- a processing device and a memory stack operatively coupled to one another and to a module board,
- wherein the memory stack includes a base die and a memory die on the base die,
- wherein the memory die includes an outer bank region, a central TSV region, first and second inner bank regions, and
- a first non-central TSV region, and
- wherein the central TSV region is disposed between the outer bank region and the second inner bank region, and the first non-central TSV region is disposed between the first inner bank region and the second inner bank region.
A semiconductor module comprising:
- a processing device and a memory stack operatively coupled to one another,
- wherein the memory stack includes:
- a plurality of memory dies stacked on a base die;
- and
- a plurality of TSVs penetrating the memory dies,
- wherein the base die includes a circuit occupied region, a central TSV occupied region, a non-central TSV occupied region and a PHY occupied region,
- wherein a first distance from the processing device to the circuit occupied region is longer than a second distance from the processing device to the central TSV occupied region,
- a third distance from the processing device to the non-central TSV occupied region is shorter than the second distance, and
- a fourth distance from the processing device to the PHY occupied region is shorter than the second distance and greater than the third distance.
A semiconductor module comprising:
- a processing device and a memory stack operatively coupled to one another,
- wherein the memory stack includes a base die, memory dies stacked on the base die, and central and non-central TSVs that vertically penetrate the memory dies,
- wherein at least one of the memory dies includes outer and inner banks, and a first electrical path that is electrically coupled to the outer bank through the central TSV from the processing device is longer than a second electrical path that is electrically coupled to the inner bank through the non-central TSV from the processing device.
A semiconductor module comprising:
- a memory stack including a base die, a plurality of memory dies stacked on the base die, at least one central TSV and at least one non-central TSV penetrating the memory dies,
- wherein each of the memory dies includes an outer bank and at least one inner bank, and
- a processing device operatively coupled to the memory stack via a first electrical path to the outer bank and to the inner bank of each memory die and to the at least one inner bank via a second electrical path,
- wherein the first electrical path includes the at least one central TSV, and
- wherein the second electrical path includes the at least one non-central TSV.
Dependencies are inferred from the claim text.